Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Agilent Technologies, Inc.

Other

Ted B Ziemkowski

John G McBride

Heather Noel Bean

David Kay Campbell

Mark John Bianchi

Gregory A Hill

Daniel E Yee

Chris Corman

A laser maze attraction has a series of lasers and sensors that may be configured in a maze where a user may be timed for completing the maze, but with penalties for breaking a laser beam. A controller may illuminate a plurality of lasers and monitor sensors corresponding to each of the lasers. The controller may also calculate an elapsed time and deduct a penalty for any laser beam that is broken. A customer interface may include a timer, various buttons arranged in the maze, and other devices that may be actuated during the timed event.

Laser maze

Image stabilizing in cameras is disclosed. In an exemplary implementation, a camera system may comprise an image sensor for collecting image data during use, and a motion sensor generating at least camera roll data. An image stabilizing subsystem may be operatively associated with the motion sensor and the image sensor. The image stabilizing subsystem moves the image sensor based on the camera roll data from the motion sensor and a correction factor based on a calibration procedure and stored in the image stabilizing subsystem to correct for at least camera roll during image exposure. Methods of calibrating a camera system for camera roll and of reducing blur from camera roll during use are also disclosed.

Image stabilizing in cameras

A system for synchronizing the exposure of an image by a master camera with the exposure of an image by one or more slave cameras, each of which is located at a different position relative to a common subject to be photographed. Exposure synchronization is accomplished via an optical sensing system on each slave camera that detects a light pulse (e.g., a flash or strobe) from the master camera emitted simultaneously with the initiation of the exposure of the subject, causing the slave camera to trigger an exposure of the subject, if the detected light pulse is within the parameters of the image capture mode manually selected for a given camera. An image may thus be captured from each of the different angles, relative to the subject being photographed, at which the cameras are positioned.

System for near-simultaneous capture of multiple camera images

A connector, particularly suited for use in a digital camera, having electrostatic discharge features that prevent the occurrence of electrostatic discharge events. The connector comprises a printed circuit board that includes a ground contact, a power contact, and a plurality of signal contacts that are offset from an edge of the printed circuit board. A row of vias are disposed between the signal contacts and the edge of the printed circuit board, and adjacent opposite sides of each of the signal contacts, that attract electrostatic energy before it can reach the signal contacts. The signal contacts have different lengths and shapes, depending upon their purpose. An electrostatic discharge protection method and digital camera are also disclosed.

Method and edge connector providing electrostatic discharge arrest features and digital camera employing same

A method for manufacturing a surface mount solder pad that is adapted to function as a heat sink for an electronic component soldered to the pad. The method comprises a step of providing a printed wiring board having a conductive layer disposed thereon. The method further comprises a step of selecting a size and arrangement of regions of a solder pad so as to sink sufficient heat. The method also comprises removing non-selected regions of the conductive layer to produce solder pads on the surface of the printed wiring board enhanced with features that promote heat transfer to sink enough heat generated by one of the surface mount components to provide for its proper operation.

Method for making a printed wire board having a heat-sinking solder pad

A battery management system and method for an electronic device that may be powered by an AC source (using an AC adapter), or by a battery. The battery management system includes firmware configured to determine whether a battery coupled to the electronic device is rechargeable. The firmware is also coupled to and configured to control a charge switch. When the battery and an AC source are both coupled to the device, activating the charge switch causes a charging current to be applied from the AC source to the battery. The charge switch and firmware are configured to cause the charging current to not be applied to the battery if it is determined that the battery is not rechargeable.

In-device charging system and method for multi-chemistry battery systems

A surface mount solder pad that is adapted to function as a heat sink for an electronic component soldered to the pad. Included is a printed wiring board having solder pads disposed on its surface that are adapted for soldering to leads of surface mount components. The solder pads are electrically interconnected by conductive traces also disposed on the surface. At least one of the solder pads has an enhanced surface area that is selected larger than necessary for the soldering, and that is selected sufficiently large so as to sink enough heat generated by one of the surface mount components to provide for its proper operation.

Apparatus and method for adapting surface mount solder pad for heat sink function

A bidirectional asynchronous open collector buffer. The buffer employs set delays and control logic to prevent latch up of the buffer when the low signal is applied to one of the ports of the buffer. Additionally, the buffer employs reset delays in conjunction with the control logic for suppressing oscillation of the buffer when one of the ports of the buffer is released from the applied low signal.

Bidirectional asynchronous open collector buffer

A switching multiplexor arrangement of relays having configuration flexibility and operative for balancing thermal offset of the relays Accumulated thermal offset of the relays along the various propagation paths through the multiplexor is balanced, by maintaining equal numbers of configured relays, along the various propagation paths, so that there are substantially equal amounts of accumulated thermal offset for the various propagation paths.

Switching multiplexor arrangement of relays for balancing thermal offset

A cache output selector for a multi-way set-associative cache memory which provides for simultaneous access of multiple-word data is presented. The cache memory comprises a plurality of data arrays wherein no two consecutive multiple-word reside in the same data. The cache output selector of the present invention includes, for each data array of the plurality of data arrays, a qualifying multiplexor which receives the respective tag match signals from each of the tag matching circuits as data input and a set selector signal, as selector input, and at least one qualifying signal as qualifying input. The set selector signal indicates which data array a first set of the multi-way set-associative memory resides in during a current read/write cycle. The qualifying multiplexor combines a clock qualifying functionality and a multiplexor functionality to produce a data array output enable signal in only two levels of logic. The cache memory comprises a prefetch buffer path and a bypass path from which the cache output selector selects an addressed multi-word for output. The output path selected circuit includes a pair of qualifying NOR gates. Each qualifying NOR gate combines a clock qualifying functionality and a logical NOR functionality to produce a qualified prefetch buffer path output enable signal and a qualified bypass path output enable signal respectively.

Speed efficient cache output selector circuitry based on tag compare and

Disclosed herein are methods and apparatus relating to speed optimal bit ordering in a cache memory. All of the data arrays capable of driving a single output bit are grouped with combinational I/O logic for driving same. The data arrays and combinational I/O logic corresponding to a single output bit can be thought of as a bit slice of a cache. Bit slices are preferably arranged so that predecode bit slices are nearest to the I/O end of the cache. A number of predecode bit slices corresponding to a single instruction or data word are preferably followed by the instruction's predecode data bit slices. Non-predecode data bit slices are arranged so that big/little endien data bit pairs are adjacent to one another, or as close to each other as possible given other bit slice ordering restraints. The arrangement of bit slices in big/little endien pairs yields I/O buses of minimum length. Components of combinational I/O logic are arranged in staggered form, perpendicularly to the I/O datapath of a cache. In this manner, a single control line can latch all of the elements in a logical register.

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Loveland, CO, United States of America

Ted B Ziemkowski