International Business Machines Corporation

Ted A Rehage

Frankie Sherwood Shook

William C Dodt

Kenneth A Bushaw

Charles R Kirkpatrick

Francis L Robinson

George A Bigelow

William K Taylor

Wayne J Bauer

William I Branson

Paul J Curlander

A document distribution terminal is organized with two supervisory processing units, one to control the data entry and data printing and the other to control the terminal. Each of these processing units only performs control functions. All of the data processing is performed by various specialized devices preparing the document data for transmission or for printing. Further, the terminal is organized with two interfaces and an adapter coupling the two interfaces. The terminal-controlling processing unit supervises one interface that interconnects all of the specialized devices. The other processing unit, that controls the data entry and data printing devices, supervises the second interface. Once the supervisory processing units have set up a job in the terminal, the data transfer across the two interfaces is substantially under the control of logic in the adapter.

Modular, processor-controlled document distribution terminal

A peripheral system has one or more buffered control units connected to a plurality of peripheral devices. Operation times of the devices are marked by the buffer and controls which overlap device operations, queue device operations in a priority set of queues, and prioritize peripheral system operations. Plural specialized interconnections between each control unit and the devices include a preparatory connection for transfer of preparatory commands to devices, a tag or control connection for device selection, deselection and control and a data-command connection for signal transfers between a selecting control unit and a selected peripheral device.

Buffered peripheral system with priority queue and preparation for

A buffer storage apparatus has two buffers alternating between receiving and supplying data signals. The buffer functions are alternated between the buffers when one of the buffers is empty and another one of the buffers has received a predetermined number of signals even though that data-receiving buffer is not yet full. With data transferred in blocks of data bytes, switching between buffers occurs on the predetermined address boundaries of the data blocks. Alternation of functions between the buffers can occur at any one of a plurality of address boundaries within the data-receiving one of the buffers. By using a plurality of such buffer storage apparatus to connect individual data burst units to a plural-port high-speed common unit, each data burst unit has a high speed buffered access to the high speed common unit.

Alternating data buffers when one buffer is empty and another buffer is

In a plural unit system, particularly of the data processing type, controlled units such as tape drives, constitute status reporting units (SRUs) which report status including error conditions to one or more status analyzing units such as computers (CPUs), programmable controllers, and the like. Each of the SRUs has a register, such as a shift register, associated therewith for receiving error status indications. The signal state of the shift register when all zeros indicates error-free status, any nonzero state signifies an error. An OR circuit receives signals from all of the bit positions of each of the respective shift registers and combines same into an SRU group error indicating signal. A second register, also a shift register, associated with the respective SRUs receives the output of the OR circuit in one of its bit positions, the bit position indicating the address of the reporting SRU. The output of the two shift registers associated with each of the SRUs are serialized onto one wire and supplied to an intermediate shift register. Combined signal status in the intermediate shift register are then supplied to one or more status analyzing units in a two byte format, i.e., one byte for the address and a second byte for the error status. An appropriate status analyzing unit then determines the error condition of the SRU. If more than one SRU is in error, then the address byte will have more than one binary one indicating state requiring further analysis by the respective status analyzing units.

Status reporting

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Longmont, CO, United States of America

Ted A Rehage