Other

Chartered Semiconductor Manufacturing Ltd (corporation)

Teck Koon Lee

Lap Chan

Cher Liang Cha

Chock Hing Gan

Eng Fong Chor

Gong Hao

Po-Ching Liu

Formation of a MOSFET with a polysilicon gate electrode embedded within a silicon trench is described. The MOSFET retains all the features of conventional MOSFETs with photolithographically patterned polysilicon gate electrodes, including robust LDD (lightly doped drain) regions formed in along the walls of the trench. Because the gate dielectric is never exposed to plasma etching or aqueous chemical etching, gate dielectric films of under 100 Angstroms may be formed without defects. The problems of over etching, and substrate spiking which are encountered in the manufacture of photolithographically patterned polysilicon gate electrodes do not occur. The entire process utilizes only two photolithographic steps. The first step defines the silicon active area by patterning a field isolation and the second defines a trench within the active area wherein the device is formed. The new process, uses the same total number of photolithographic steps to form the MOSFET device elements as a conventional process but is far more protective of the thin gate oxide.

Embedded polysilicon gate MOSFET

A method of forming trenches having different depths for use in shallow trench isolations is achieved. Dishing problems due to isolation oxide thinning over wide trenches is eliminated. A silicon substrate is provided. A pad oxide is grown. A polishing stop of silicon nitride is deposited. An oxide layer is grown overlying the silicon substrate. The oxide layer, polishing stop layer, and pad oxide layer are etched through to the silicon substrate to form openings for planned first trenches. A polysilicon layer is deposited overlying the oxide layer and filling the openings for the planned first trenches. The polysilicon layer is polished down to the top surface of the oxide layer such that the polysilicon layer remains only in the openings of the planned first trenches. The oxide layer, polishing stop layer, and pad oxide layer are etched through to the silicon substrate to form openings for planned second trenches. The silicon substrate and the polysilicon layer are simultaneously etched to complete the first trenches and the second trenches, with the second trenches deeper than the first trenches, and with the oxide layer a hard mask, and the integrated circuit device is completed.

Method to form narrow and wide shallow trench isolations with different trench depths to eliminate isolation oxide dishing

A method of fabricating a MOSFET device, in which a source and drain region has been formed, prior to the formation of an ion implanted channel region, has been developed. The early creation of source and drain region allows a high temperature anneal to be performed, removing damage resulting from the source and drain ion implantation procedures, however without redistribution of channel dopants. The method features creating an opening in an insulator layer, after the source and drain formation, and then forming the channel region in the semiconductor substrate, directly underlying the opening in the insulator layer. A polysilicon gate structure is next formed in the opening, resulting in self-alignment to the underlying channel region.

Creation of a self-aligned, ion implanted channel region, after source

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Singapore, Singapore

Teck Koon Lee