Intel Corporation

Tea M Lee

Robert R Fulton

Chinnugounder Senthilkumar

Andrew M Volk

Jien-Hau Ng

Ronald W Swartz

Harishankar Sridharan

An apparatus and a method are provided for selectively enabling and disabling a squelch circuit in a Serial Advanced Technology Attachment (SATA) host or SATA device while maintaining proper operation of the host and device. An apparatus and method are provided which allow the squelch circuit to be selectively enabled and disabled across SATA power states (PHY Ready, Partial, and Slumber) and in Advanced Host Controller Interface (AHCI) Listen mode.

Apparatus and method for selectively enabling and disabling a squelch circuit across AHCI and SATA power states

A bias circuit includes multiple output legs. During a transition from a low power state to an operational state, multiple output legs are turned on to provide a bias voltage. After a suitable period, at least one of the multiple output legs is turned off.

Driver circuit bias control

Circuitry for controlling the oscillation frequency of an oscillator by using a digitally tunable on-chip capacitor bank. The capacitor bank includes a plurality of on-chip capacitors, each of which is independently selectable by a control signal for providing a selectable amount of capacitance to the oscillator to control the oscillator's oscillation frequency.

Oscillator with tunable capacitor

A circuit for producing a reliable duty cycle for a low power oscillator. The circuit produces a square wave signal based on the differences between the oscillating output signal driven by a piezoelectric crystal and a phase shifted output signal. This circuit provides a quick start for a clock signal, generates a reliable fifty percent duty cycle and is better protected from common mode noise. This circuit can also be configured to be programmable to provide for an adjustable duty cycle.

Duty cycle tuner for low power real time clock oscillator

A clock oscillator circuit that includes an inverting amplifier and a resonator configured to generate an oscillating signal. The clock oscillator includes a bias circuit having a relatively constant current source configured to create a bias voltage to bias the amplifier in an operating state that can sustain the oscillating signal. The inverting amplifier and the bias circuit are configured to operate in a low power state.

Low power self-biasing oscillator circuit

An oscillator circuit including an integrated circuit amplifier, an integrated circuit active resistance circuit to set the gain of the amplifier, a crystal resonator to set the frequency of the signal generated by the oscillator circuit, and a pair of capacitors respectively situated at the inputs and outputs of the amplifier to assist in the starting of the oscillation signal. The active resistance circuit is responsive to an input signal in order to set the gain of the amplifier slightly above unity gain in order to meet the criterion for oscillation, but not too much above unity gain where the oscillator would unduly consume too much power. Thus, the oscillator has inherent low power characteristics. The active resistance circuit allows the amplifier gain to be set by software or other electronic means.

Growing community of inventors

Federal Way, WA, United States of America

Tea M Lee