United Microelectronics Corp.

Faraday Technology Corporation

Te-Sun Wu

Chen-Chiu Hsue

Ming-Tzong Yang

Hsin-Li Chen

Stephen S Fu

Han-Shen Lo

Chih-Hung Chen

Heng-Sheng Huang

Kun-Luh Chen

Chih-Kang Chiu

Heng Sheng Huang

Hui-Fang Tsai

Sheng-Tai Young

Tsun-Zu Lin

Tsung-Yuan Lee

Kun-Lun Chen

Kai-Chi Hsieh

A high density read-only memory (ROM) cell is installed on a silicon substrate for storing data. The ROM cell includes a first doped region being of a second conductive type installed on the silicon substrate, a plurality of first heavily doped regions being of a first conductive type installed in the first doped region, a second doped region being of the second conductive type installed on the silicon substrate, and a gate installed on the surface of the silicon substrate and adjacent to the first doped region and the second doped region.

High density ROM cell

A wafer level burn-in method for static-random access memory. The SRAM memory has a plurality of word lines and a plurality of bit lines. The SRAM memory also has pull up circuits and equalizer circuits connected to various bit lines. All the word lines are switched on for testing any leakage in the gate dielectric layer. A high potential is applied to a bit line of every bit line pairs and a low potential is applied to the other bit line of the bit line pairs. The pull-up circuits and the equalizer circuits are shut down. The current at a steady state is used to judge the normality of an SRAM chip.

Wafer level burn-in of SRAM

A voltage-reducing device of low power dissipation is provided, including a plurality of transistors, which are self-connected as diode equivalent. These transistors are then cascaded in series in the same direction and coupled to a voltage source. Since every transistor has a threshold voltage, the voltage at the end of the forward-biased cascaded transistors will be lowered than the voltage source so as to provide a reduced voltage source. Furthermore, since the voltage adjustment of the device is based on the threshold voltage, there is hardly any power dissipation. In addition, we can use different threshold voltages from various transistors to provide different combinations of these threshold voltages to obtain the desired voltage drop.

Voltage-reducing device with low power dissipation

The ROM device comprises a number of memory cells each is constructed based on a MOS transistor, the memory cells in the ROM are arranged into a number of rows and a columns. A number of word lines each connects to the gates of each of the MOS transistors of all the memory cells in each of the rows. A number of bit lines each connects to one of the source/drain pair of each of the MOS transistors of all the memory cells in each of the columns. A multiplexer comprises a number of transmitting transistors, each of the transmitting transistors is connected to a corresponding one of the bit lines, forming a current flow path including the transmitting transistor, the connected bit line, and the memory cells correspondingly connected to the bit line. A sense amplifier is coupled to the multiplexer for sensing the current flowing therethrough the current flow path to output a corresponding sense output signal. The method for bypassing null-code sections to comprise programing the transmitting transistor in the current flow path into an off status when all memory cells in the column connecting to the bit line of the transmitting transistor is required to contain null code.

Method for bypassing null-code sections for read-only memory by access

A ROM is formed by depositing a first layer composed of a material selected from polysilicon and polycide on the substrate, patterning the first layer by masking and etching, depositing a dielectric layer over the first layer and patterning the dielectric layer and the first layer into the pattern of first conductor lines, forming a contact window through the dielectric layer down to the substrate, depositing a second layer composed of a material selected from polysilicon and polycide on the device and forming second conductor lines directed orthogonally to the first conductor lines formed from the first layer, and ion implanting into the substrate through the second layer to form a contact region electrically connected to the second conductor lines of the second layer.

High density ROM

A voltage detector for determining the high or low status of a power supply output voltage, including a front-end detector and an inverting amplifier. The front-end detector includes a number of NMOS and PMOS transistors which constitute active loads. The voltage detector is inherently independent of device fabrication condition changes, as well as on the temperature variations.

Power supply voltage detector

A ROM array with coding after metallization comprises a plurality of first bit lines, a plurality of second bit lines, a plurality of third bit lines, a plurality of word lines, a plurality of first control lines, a plurality of second control lines and a plurality of selecting lines. Memory cells of the ROM array are formed by the intersection of the word lines and the first and second bit lines, wherein the word lines are polysilicon gates and the bit lines are drain/source diffusion regions. The third bit lines are metal lines above the first bit lines. The third bit lines are not wide enough to cover spacings between the first and second bit lines, thus exposing spaces for code implantation. The first and second control lines intersect the first and second bit lines to form a number of switches for controlling data reading paths to The memory cells. The positions and ON/OFF states of the switches are designed to provide at least two data reading paths to each memory cell. Thus, the sensing currents in the bit lines are increased and become more uniform.

Read-only-memory array with coding after metallization

A read only memory cell array and method of operation thereof comprises an array of memory transistor cells, a plurality of word lines, a plurality of bit lines, a plurality of select bit lines, a plurality of bank select lines for enabling reading of a selected bank in the array connected to bank select transistors in the bank, a select even line adapted for enabling reading of even cells in a selected bank connected to select even cell transistors in the bank, and a select odd line adapted for enabling reading of odd cells in a selected bank connected to select odd cell transistors in the array.

High density ROM with select lines

A mask ROM device having active bit-line clamp circuits which employ a voltage-to-current converter as the clamp circuit for selectively coupling a main bit line of the ROM memory device to a selected one of virtual ground lines. The voltage-to-current converter is selectively coupled between the main bit line and a first or second virtual ground line for clamping therebetween. The voltage-to-current converter converts the voltage difference between the coupled main bit line and the selected first or second virtual ground line into a corresponding current in proportion to a voltage difference, the converted current being coupled to the selected first or second virtual ground line.

Active bit-line clamp circuit for flat cell structure of mask read-only

Method of manufacturing a high density ROM

A cost-effective and manufacturable method for producing ROM integrated circuits with closely-spaced self-aligned conductive lines, on the order of 0.3 micrometers apart, is described. Parallel, conductive semiconductor device structures are formed in a semiconductor substrate. An insulating layer is formed over the semiconductor substrate. A first conductive polysilicon layer is formed over the insulating layer. The first conductive polysilicon layer is patterned to form first polysilicon conductor lines which are parallel to each other, and orthogonal to the parallel, conductive semiconductor device structures. A first silicon oxide layer is formed on and between the first polysilicon conductor lines. The first silicon oxide layer is anisotropically etched to produce sidewall structures on the first polysilicon conductor lines. A second silicon oxide layer is formed on and between the first polysilicon conductor lines. A second conductive polysilicon layer is formed over the first polysilicon conductor lines and in openings between the first polysilicon conductor lines. The second conductive polysilicon layer is etched back to form second polysilicon conductor lines, parallel to, between and self-aligned with the first polysilicon conductor lines, and separated from the first polysilicon conductor lines by width of the sidewall structures.

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Hsin-Chu, Taiwan

Te-Sun Wu