Novatek Microelectronics Corp.

Te-Lin Ping

I-Huan Huang

Yao-Cheng Chuang

Shi-Yen Huang

Han-Chiang Su

A computer system architecture including a first buffer, a second buffer, a sub-system and a CPU is provided. The sub-system carries out a first task to obtain first returned information, stores the first returned information in the first buffer and sets up a first occupancy flag to the first buffer. Next, the sub-system carries out a second task to obtain second returned information, stores the second returned information in the second buffer, and sets up a second occupancy flag to the second buffer. The CPU reads the first returned information and eliminates the first occupancy flag. After the second returned information is stored in the second buffer and the first occupancy flag is eliminated, the sub-system continuously carries out a third task to obtain third returned information, stores the third returned information in the first buffer, and sets up the first occupancy flag to the first buffer.

Computer system architecture

An adaptive memory address translation method includes the following steps. Multiple request instructions are received. A memory address corresponding to each request instruction includes a bank address. The memory addresses corresponding to the request instructions are translated, such that the bank addresses corresponding to at least one part of the any two adjacent request instructions are different. A numerical translation is utilized to translate the memory addresses corresponding to the request instructions, such that the memory addresses corresponding to the any two adjacent request instructions have less different bits.

Adaptive address translation method for high bandwidth and low IR concurrently and memory controller using the same

A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the one or more first request instructions and the one or more second request instructions to the memory. The control unit compares bandwidths of the one or more first request instructions with bandwidths of the one or more second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.

Memory control system and method

A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the first request instructions and the second request instructions to the memory. The control unit compares bandwidths of the first request instructions with bandwidths of the second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.

A circuit system periodically checks a system-environment monitor value, and then obtains a system-environment monitor value index corresponding to the system-environment monitor value in the environment-adjustment look-up table. Finally, the circuit system adjusts a signal delay time according to a delay adjustment value corresponding to the system-environment monitor value index.

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Te-Lin Ping