Seiko Epson Corporation

Other

Silicon Graphics, Incorporated

S-mos Systems, Inc.

Te-Li Lau

Derek J Lentz

Le Trong Nguyen

Yasuaki Hagiwara

Johannes Wang

Sanjiv Garg

Yoshiyuki Miyayama

Quang H Trang

Sze-Shun Wang

Cheng-Long Tang

Trevor A Deosaran

Linley M Young

Kian-Chin Yap

Makoto Matsubayashi

Cheryl Senter Brashears

Le-Trong Nguyen

Henry Packard Moreton

Bent Hagemark

Michael L Fuccio

Mark W Troeller

The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.

System and method for handling load and/or store operations in a superscalar microprocessor

The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across multiple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.

High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution

A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

High-performance, superscalar-based computer system with out-of-order instruction execution

A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

Microprocessor architecture capable of supporting multiple heterogeneous processors

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

Growing community of inventors

Palo Alto, CA, United States of America

Te-Li Lau