Advanced Micro Devices Corporation

Ati Technologies Ulc

Te-Hsuan Chen

Richard Thomas Schultz

Russell J Schreiber

Eric W Busta

Regina Tien Schmidt

Aaron Keiichi Horiuchi

Donald A Clay

Catherina Simona Matheis Ionescu

Stephen J Dussinger

Michael Edward Griffith

Derek P Peterson

Chu-Wen Wang

Hye Jung Stanford

Ruochen Xie

Elizabeth C Conrad

Kathryn E Wilcox

William Edwin Laub, Jr

A system and method for efficiently designing a through silicon via (TSV) macro blocks are described. In various implementations, the circuitry of a processor executes instructions of a place and route tool that provides automatic placement of macro blocks and standard cells on an integrated circuit die based on a copy of a netlist of the integrated circuit being designed and a copy of a standard cell library that includes a variety of standard cells and macro blocks. The processor places two functional macros in the floorplan with a channel between them. In the channel, the processor places a TSV macro that includes at least one boundary cell inside of the TSV macro. The processor prevents placement of a boundary cell adjacent to at least one side of the TSV macro despite empty space exists due to no standard cells or macros about the at least one side.

Through silicon via macro with dense layout for placement in an integrated circuit floorplan

Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.

Power grid layout designs for integrated circuits

Growing community of inventors

Waltham, MA, United States of America

Te-Hsuan Chen