Taiwan Semiconductor Manufacturing Comp. Ltd.

Te-Hsin Chiu

Jiann-Tyng Tzeng

Meng-Han Lin

Shih-Wei Peng

Wei Cheng Wu

Wei-Cheng Lin

Wei-An Lai

Kam-Tou Sio

Wei-Cheng Wu

Meng-Hung Shen

Li-Feng Teng

Te-An Chen

Chien-Hung Chang

Ching-Wei Tsai

Chia-Tien Wu

Hou-Yu Chen

Yu-Xuan Huang

Kuan-lun Cheng

Chung-Hsing Wang

Shang-Wei Fang

Jiun-Wei Lu

Wei-cheng Wu

A semiconductor device and a method of manufacturing the device are disclosed. In one aspect, the semiconductor device includes a first active region that extends along a first lateral direction and includes a plurality of first epitaxial structures. The semiconductor device also includes an interconnect structure that also extends along the first lateral direction and is disposed below the first active region, wherein at least one of the plurality of first epitaxial structures is electrically coupled to the interconnect structure. The interconnect structure includes at least a first portion that offsets from the first active region along a second lateral direction perpendicular to the first lateral direction.

Semiconductor devices and methods of manufacturing thereof

A method includes doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface.

A semiconductor device includes a semiconductor substrate. The semiconductor device includes a first fin protruding from the semiconductor substrate and extending along a first direction. The semiconductor device includes a second fin protruding from the semiconductor substrate and extending along the first direction. A first epitaxial source/drain region coupled to the first fin and a second epitaxial source/drain region coupled to the second fin are laterally spaced apart from each other by an air void.

Multiple back side/buried power rail (BPR) cell including field-effect transistors with air void between two adjacent BPR cells

A semiconductor device includes a first transistor and a second transistor. The first transistor is of a first type in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is of a second type arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device further includes a first conductive line in a third layer between the first and second layers. The first conductive line electrically connects a first source/drain region of the first active region to a second source/drain region of the second active region. The gate comprises an intermediate portion disposed between the first active region and the second active region, wherein the first conductive line crosses the gate at the intermediate portion.

Semiconductor structure and method of forming the same

An integrated circuit (IC) device includes a first plurality of active areas extending in a first direction and having a first pitch in a second direction perpendicular to the first direction, and a second plurality of active areas extending in the first direction, offset from the first plurality of active areas in the first direction, and having a second pitch in the second direction. A ratio of the second pitch to the first pitch is 3:2.

Hybrid cell-based device, layout, and method

An IC package includes a first die including a front side and a back side, the front side including a first signal routing structure, the back side including a first power distribution structure, and a second die including a front side and a back side, the front side including a second signal routing structure, the back side including a second power distribution structure. The IC package includes a third power distribution structure positioned between the first and second power distribution structures and electrically connected to each of the first and second power distribution structures.

Power distribution structure and method

A method of making an integrated circuit includes steps of etching an opening in an insulating mask to expose a first dummy contact on a backside of the integrated circuit, depositing a conductive material into the opening, the conductive material contacting a sidewall of the first dummy contact, and recessing the conductive material to expose an end of the first dummy contact. The method also includes steps of depositing an insulating material over the conductive material in the opening, removing the first dummy contact from the insulating mask to form a first contact opening, and forming a first conductive contact in the first contact opening, the first conductive contact being electrically connected to the conductive material.

Integrated circuit with backside interconnections and method of making same

A method for fabricating a semiconductor structure includes depositing a first insulation material over a substrate, wherein the substrate includes an active region. The method further includes etching the first insulation material to define a first recess extending along a first direction at a first level of the first insulation material. The method further includes depositing a second insulation material lining with a sidewall of the first recess. The method further includes depositing a first metal line in the first recess.

Manufacturing method for semiconductor device

A method of fabricating an integrated circuit includes fabricating a set of transistors in a front-side of a substrate, fabricating a first set of vias in a back-side of the substrate, depositing a first set of conductive structures on the back-side on a first level, depositing a second set of conductive structures on the back-side on a second level thereby forming a set of power rails, fabricating a second set of vias in the back-side, and depositing a third set of conductive structures on the back-side on a third level. The first set of vias is electrically coupled to the set of transistors. The second set of vias is electrically coupled to the first and third set of conductive structures. A first structure of the first set of conductive structures is electrically coupled to a first via of the first set of vias.

Integrated circuit, system and method of forming same

A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Array boundary structure to reduce dishing

A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.

Memory device and layout, manufacturing method of the same

A semiconductor device and a manufacturing method thereof are provided. The method includes forming an isolation structure in a substrate to define an isolating region and forming a capacitor structure on an upper surface of the isolation structure and comprising a first semiconductor structure and a second semiconductor structure separated by an insulator pattern. The first semiconductor structure and the second semiconductor structure are formed with upper surfaces aligned with one another.

Semiconductor device having capacitor and manufacturing method thereof

Fin field-effect transistor and method of forming the same

An integrated circuit structure is disclosed, including a gate, a first conductive line and a pair of second conductive lines, and a first feed-through via. The gate is disposed on a front side of the integrated circuit structure and extends in a first direction on a first side of a dielectric layer. The first conductive line and a pair of second conductive lines are disposed on a second side, opposite of the first side, of the dielectric layer and on a back side, opposite of the front side, of the integrated circuit structure. The first conductive line is interposed between the pair of second conductive lines in a layout view. The first feed-through via extends through the dielectric layer in a second direction different from the first direction. The first feed-through via couples the gate to the first conductive line.

Integrated circuit structure

In some embodiments, a method of making a semiconductor device includes forming a recess in a first region of a first dielectric material, the first dielectric material at least partially embedding a semiconductor region, the recess having a first surface portion separated by a distance in a first direction from the semiconductor region by a portion of the first dielectric material; depositing a second dielectric material in the recess to form a second surface portion oriented at an oblique angle from the first surface portion; and depositing a conductive material in the recess. In some embodiments, the method further includes partially exposing the semiconductor region in a second recess in the first dielectric material and selectively depositing the second dielectric material on the first dielectric material, but not the semiconductor region, in the second recess.

Growing community of inventors

Miaoli County, Taiwan

Te-Hsin Chiu