Taiwan Semiconductor Manufacturing Comp. Ltd.

Te-Fu Tseng

Hung-Jen Hsu

Chih-Kung Chang

Fu-Tien Weng

Yi-Ming Dai

Yu-Kung Hsiao

Chin Chen Kuo

Chin-Chen Kuo

Chung-Sheng Hsiung

Chun-Chieh Chang

Bii-Junq Chang

Chao-Yi Lan

Yu-Jen Yu

Jack Deng

Chi-Hung Liao

Sheng-Liang Pan

Cheng-Yu Chu

Fu-Tien Wong

Chai-Der Chang

Chiung-Yuan Chang

Po-Wen Lin

A method is provided for processing a substrate. The substrate has at least one filter region, a plurality of bond pads, and a plurality of scribe lines arranged around the filter region and bond pads. A first planarization layer is formed above the substrate. The planarization layer has a substantially flat top surface overlying the filter region, the bond pads and the scribe lines. At least one color resist layer is formed over the first planarization layer and within the filter region while the first planarization layer covers the bond pads and the scribe lines.

Image sensor

Image sensor fabrication method and structure

A method for processing a semiconductor substrate includes providing a substrate having at least one filter region with a plurality of bond pads in it. Metal is deposited above the bond pads, to reduce the bond pad step height. A planarization layer is formed such that the deposited metal has a height near to a height of the planarization layer. At least one color resist layer is formed above the planarization layer.

A color filter includes a substrate having a plurality of scribe lines arranged to form at least one filter region surrounded by the scribe lines. The scribe lines are at least partially filled with a resist material. At least one color resist layer is formed above the substrate within the at least one filter region.

Color filter with resist material in scribe lines

A method of fabricating microlens devices. The method includes filling the bond pad areas and scribe lines, or other areas, to improve the topography of the semiconductor wafer surface. A microlens material is applied to the surface after the bond pad areas and scribe lines have been filled. Because of the improved topography, the thickness of the microlens material is more uniform, thereby facilitating the formation of uniformly shaped microlenses.

Method for fabricating microlens with lithographic process

A method for fabricating a microelectronic product provides for forming a planarizing layer upon a bond pad and a topographic feature, both formed laterally separated over a substrate. The planarizing layer is formed with a diminished thickness upon the bond pad such that it may be readily etched to expose the bond pad while employing as a mask an additional layer formed over the topographic feature but not over the bond pad. The method is particularly useful for forming color filter sensor image array optoelectronic products with attenuated bond pad corrosion.

Method for fabricating microelectronic product with attenuated bond pad corrosion

An improved method for depositing the polysilicon layer from which a gate pedestal is later formed is described. Deposition takes place in two stages. Initially, the conventional deposition temperature of about 630&deg; C. is used. Then, when the intended thickness of polysilicon has been grown, the temperature is ramped down to about 560&deg; C., without interrupting the deposition process, and growth of the film continues to completion. This is followed by a standard doping step using POCl . Polysilicon films formed in this way have been found to have very smooth surfaces because the topmost layer is less subject to uncontrolled grain growth. As a consequence, dielectric layers obtained by oxidizing such films exhibit superior breakdown voltages.

Polysilicon layer having improved roughness after POCl3 doping

A method for developing a semiconductor device low resistance electrical contact is described. In this process a gate oxide layer followed by a polysilicon layer is deposited on the semiconductor substrate in proximity to the device contact area. It is subsequently patterned with photoresist and etched to produce the desired gate structure. This is followed by a deposited layer of silicon dioxide or silicon nitride (SIN) which is appropriately patterned and etched to form gate isolation spacers. Then a nominal 300 &angst; layer of silicon nitride (SIN) is deposited followed by a layer of tetraethyl orthosilicate (TEOS) or borophosphosilicate glass (BPSG). The contact area is defined by photolithography, and the passivation layers are etched either by a dry etch such as a RIE process, or a combination of a wet BOE process followed by a dry etch, to form the metal contact holes. Prior to sputtering the contact metal, the contact area is cleaned with a 30 second dip in a BOE solution, followed by a Hydrogen Peroxide (H,O,) dip. This H,O,cleaning step enables lower device contact resistance for the P&plus; contact areas.

Method to reduce device contact resistance using a hydrogen peroxide treatment

An improved method for depositing the polysilicon layer from which a gate pedestal is later formed is described. Deposition takes place in two stages. Initially, the conventional deposition temperature of about 630.degree. C. is used. Then, when the intended thickness of polysilicon has been grown, the temperature is ramped down to about 560.degree. C., without interrupting the deposition process, and growth of the film continues to completion. This is followed by a standard doping step using POCl.sub.3. Polysilicon films formed in this way have been found to have very smooth surfaces because the topmost layer is less subject to uncontrolled grain growth. As a consequence, dielectric layers obtained by oxidizing such films exhibit superior breakdown voltages.

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Hsin-Chu, Taiwan

Te-Fu Tseng