Taiwan Semiconductor Manufacturing Comp. Ltd.

Te-En Cheng

Wei-Ken Lin

Chung-Chi Ko

Wan-Yi Kao

Hsiang-Wei Lin

Shu Ling Liao

Li Chun Te

Guan-Yao Tu

Chi On Chui

Wei-Yang Lee

Yung-Cheng Lu

Tien-I Bao

Kai-Hsuan Lee

I-Hsieh Wong

Chih-Hung Nien

Chun-Te Li

Wei-Chun Tan

Yung-Hui Lin

Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

Low-K feature formation processes and structures formed thereby

A method of forming a semiconductor device includes forming a sacrificial layer over a first stack of nanostructures and an isolation region. A dummy gate structure is formed over the first stack of nanostructures, and a first portion of the sacrificial layer. A second portion of the sacrificial layer is removed to expose a sidewall of the first stack of nanostructures adjacent the dummy gate structure. A spacer layer is formed over the dummy gate structure. A first portion of the spacer layer physically contacts the first stack of nanostructures.

Nano-FET transistor with alternating nanostructures and method of forming thereof

A method includes following steps. Fins are formed over a substrate. A dummy gate structure is across the fins. A spacer layer is deposited over the dummy gate structure. The spacer layer has a first portion in a void of the dummy gate structure and a second portion outside the void of the dummy gate structure. The second portion of the spacer layer is treated to have a different material composition than the first portion of the spacer layer, and is then etched to form gate spacers on sidewalls of the dummy gate structure. An etching process is performed on the dummy gate structure to form a gate trench between the gate spacers. The etching process etches the first portion of the spacer layer at a faster etch rate than etching the gate spacers. A gate structure is formed in the gate trench.

Densified gate spacers and formation thereof

Low-k feature formation processes and structures formed thereby

A method includes forming a first fin extending from a substrate, forming a first gate stack over and along sidewalls of the first fin, forming a first spacer along a sidewall of the first gate stack, the first spacer including a first composition of silicon oxycarbide, forming a second spacer along a sidewall of the first spacer, the second spacer including a second composition of silicon oxycarbide, forming a third spacer along a sidewall of the second spacer, the third spacer including silicon nitride, and forming a first epitaxial source/drain region in the first fin and adjacent the third spacer.

Semiconductor device and method

Field effect transistor and methods of forming the same are disclosed. The field effect transistor includes a gate electrode, a contact etch stop layer (CESL), an inter layer dielectric (ILD) and a protection layer. The CESL includes SiCON and is disposed on a sidewall of the gate electrode. The IDL is laterally adjacent to the gate electrode. The protection layer covers the CESL and is disposed between the CESL and the ILD.

Field effect transistor and method of forming the same

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Taoyuan, Taiwan

Te-En Cheng