Texas Instruments Corporation

Te-Chuan Hsu

Edison H Chiu

Jy-Der Tai

Quang-Dieu An

A look-ahead flag generator generates a flag signal corresponding to the occurrence of a predetermined value stored in a counter (10). The output of the counter outputs any of a plurality of values, the values including the predetermined value and at least one boundary value that is one unit of increment or decrement displaced from the predetermined value. A clock signal source (13) is coupled to a first input of the counter (10) to indicate a decrement or an increment to the value stored in the counter (10). An up/down signal source (11) is coupled to a second input of the counter to indicate whether an increment or a decrement of the stored value should be performed. Predetermined states of the up/down signal and the clock signal are operable to cause a boundary value stored in the counter (10) to be changed to the predetermined value. A predecoder (12) is coupled to an output of counter (10) for decoding the boundary value. A latch (132) stores the decoded boundary value. A gate circuit (111, 117, 139) is coupled to the latch (132), a flag signal output, the up/down signal source (11) and the clock signal source (13) and is operable to generate the flag signal in response to the stored decoded boundary value and the predetermined states of the up/down signal and the clock signal.

Look-ahead flag generator

A solid state memory system is arranged in a plurality of blocks of memory cells, the memory cells in each block arranged in columns and rows. When the memory system is addressed for a memory reference, block selection circuitry selects one block of the plurality of blocks, excluding all of the other blocks. Each block has a set of sense amplifiers, corresponding in number to the number of bits in the output word. Each sense amplifier is connected to an isolation switch. The outputs from the sense amplifiers connected to the non-selected blocks are thereby isolated from the sense amplifier outputs from the selected block to minimize loading of the sense amplifier outputs from the selected block. The memory cells in each block are interconnected by metal row conductors and by metal column conductors.

Growing community of inventors

Arlington, TX, United States of America

Te-Chuan Hsu