United Microelectronics Corp.

Te-Chang Wu

Chien-Kuo Wang

Kuey-Lung Hsueh

Yu-Ming Sun

Ta-Cheng Lin

Yuan-Tsung Lin

Chih-Yuan Chung

Wen-Ching Huang

Pei-Shin Chiu

An input/output circuit (I/O circuit) includes the following elements. An input/output pad (I/O pad) has a plurality of operation mode, including an output mode, a normal input mode and a tolerance mode of an input mode. A first control circuit provides a first control signal in response to a pad voltage of the I/O pad and a supply voltage. A first P-type transistor has a first body region to receive a first control signal. A second P-type transistor has a second body region to receive the first control signal. In the input mode, when the pad voltage is lower than or equal to the supply voltage, the I/O pad operates in the normal input mode, and, when the pad voltage is higher than the supply voltage, the I/O pad operates in the tolerance mode, and voltage of the first control signal is equal to pad voltage.

Input/output circuit

The present invention provides an electrostatic discharge (ESD) protection circuit including an ESD detection circuit and a plurality of power clamp circuits. The ESD detection circuit is electrically connected to a first high power line, a second high power line and at least one low power line, and is used to detect an ESD event occurring in the first high power line and another ESD event occurring in the second high power line. The ESD detection circuit includes a first trigger unit and a second trigger unit, electrically connected to the first high power line and the second high power line respectively. Each power clamp circuit has a trigger node, and the trigger nodes are electrically connected to the first trigger unit and the second trigger unit.

Electrostatic discharge protection circuit

A lateral silicon controlled rectifier structure includes a P-type substrate; an N-well region in the P-type substrate; a first Pdoped region in the N-well region and being connected to an anode; a P-well region in the P-type substrate and bordering upon the N-well region; a first Ndoped region formed in the P-well region and separated from the first Pdoped region by a spacing distance, the first Ndoped region being connected to a cathode; and a gate structure overlying a portion of the P-type substrate between the first Pdoped region and the first Ndoped region.

Lateral silicon controlled rectifier structure

A chip includes a core circuit, a main electrostatic discharge immunizing circuit, and a secondary electrostatic discharge immunizing circuit. The secondary electrostatic discharge immunizing circuit is disposed beneath a core power ring formed between the core circuit and the main electrostatic discharge immunizing circuit for reaching the aim of protecting the core circuit from damage by electrostatic discharges without area penalty of the chip. Both the main electrostatic discharge immunizing circuit and the secondary electrostatic discharge immunizing circuit include a power clamp and a plurality of current limiters, and keep electrostatic currents from reaching the core circuit with the aid of the power clamp.

Growing community of inventors

Hsinchu County, Taiwan

Te-Chang Wu