Novas Software, Inc.

Springsoft Usa, Inc.

Synopsys, Inc.

Tayung Liu

Yu-Chin Hsu

Furshing Tsai

KunMing Ho

Yirng-An Chen

Kai Yang

Ying-Tsai Chang

Chieh Changfan

Jun Zhao

Wells Woei-Tzy Jong

Bassam Tabbara

Ting Shih Ang

George Bakewell

Chih Neng Hsu

Scott Sandler

Example embodiments of disclosed configurations include a process (and system and non-transitory computer storage readable medium) for verifying an operation or a functionality of a design under test (DUT) through a distributed database processing system. In one or more embodiments, the emulator performs emulation of a DUT, and traces signals of the DUT based on the emulation. In one aspect, the traced signals are divided into multiple segments and are stored in the distributed database processing system in a form of key-value pairs. The distributed database processing system generates analysis segments based on corresponding segments of the traced signals and corresponding analysis rules. An analysis rule describes how to determine a particular characteristic of a corresponding segment of a signal. The distributed database processing system aggregates the analysis segments and generates a circuit analysis result indicating an aspect of the functionality of the DUT.

Circuit verification on a distributed database processing system

A debugging system produces displays in response to an IC design and results of a logic simulation of IC behavior based on the IC design. The IC design includes a hardware description language (HDL) model of the IC describing the IC as comprising cell instances communicating via data signals and power sources for supplying power to the cell instances. The IC design also includes power definition markup language (PDML) model describing a power intent of the IC design. The debugging system generates displays representing HDL code that are annotated to indicate how the power intent of the IC design described by the PDML model relates to the portion of the HDL model represented by the display. The debugging system also generates signals trace displays indicating how both the logic and power intent of the IC design affect the value of a user-selected signal at a user-selected time during the logic simulation.

Power-aware debugging

A netlist description of a circuit is processed to classify some signals of the circuit as essential signals and to classify all other signals of the circuit as non-essential signals. Thereafter when simulating behavior of the entire circuit in response to input signals supplied over some time interval, a simulator saves first simulation data representing behavior of the circuit's essential signals during the time interval. Thereafter the simulator is programmed to re-simulate behavior of only a selected subcircuit of the circuit during only a selected subinterval of the full time interval based on behavior of essential signals described by the first simulation data. During the re-simulation, the simulator saves second simulation data representing behavior of both essential and non-essential signals of the subcircuit to provide a more complete picture of the behavior of the selected subcircuit during the selected subinterval. Before the initial full-circuit simulation, each signal is classified as an essential signal when its behavior during the full-circuit simulation must be represented by the first simulation data in order to provide sufficient information to program the simulator to re-simulate the behavior any selected subcircuit during any selected subinterval. All other circuit signals are classified as non-essential signals whose behavior need not be represented by the saved first simulation data.

Incremental circuit re-simulation system

A debugger produces a display based on instructions executed by a circuit simulator or verification tool and on waveform data produced by the simulator or verification tool when executing the instructions. The instructions include a set of statements, each corresponding to a separate circuit signal generated by a circuit and each including a function defining a value of the circuit signal as a function of values of other circuit signals. The simulator evaluates the statements at various simulation times to compute signal values at those simulation times. The waveform data indicates signal values the simulator computes when evaluating the statements. The debugger display includes a set of statement event symbols, each corresponding to a separate evaluation of a statement and each positioned in the display to indicate a simulation time at which the simulator evaluated the statement. Each statement event symbol references the signal whose value is computed by the corresponding statement evaluation and indicates a value of that signal computed when the statement was evaluated. Each statement event symbol also references the other signals having values of which the statement indicates the computed signal value is a function and indicates those other signals values as of the simulation time at which the statement was evaluated.

IC behavior analysis system

A circuit simulator simulates a circuit described by a circuit logic model as having a set of clocked registers interconnected by un-clocked logic to produce waveform data indicating states of each circuit input signal and of each register output signal as functions of clock signal edge timing. The waveform data and the logic model are then processed to produce a temporal schema model characterizing the circuit's logic and behavior. A display based on the temporal schema model depicts circuit behavior using separate symbols to represent successive circuit input signal states and register output signal states at various times during the simulation. The same display also graphically depicts fan-in or fan-out logical relationships by which circuit input signal states and register output signal states influence register input signal states.

System for characterizing simulated circuit logic and behavior

Described herein is a system for verifying that a circuit described by a hardware description language file has a property of responding to an antecedent event represented by a particular pattern in its input signals by exhibiting a consequent behavior of producing a particular pattern in its output signals during a finite time following the antecedent event. The system includes a conventional circuit simulator for simulating the behavior of the circuit under conditions defined by a user-provided test bench. The simulator produces output waveform data representing the behavior of the circuit input, output and internal signals, including signals representing the circuit's state. When the output waveform data indicates the antecedent event has occurred, the system determines the current state of the circuit from the waveform data. The system then creates and analyzes a temporally expanded model of the circuit to verify whether, starting from that current state, the circuit will exhibit the consequent behavior within that finite time under all input signal conditions.

Circuit property verification system

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Sunnyvale, CA, United States of America

Tayung Liu