Intel Corporation

Tayseer Mahdi

Florian Gstrein

James M Blackwell

Eungnak Han

Gurpreet Singh

Marie Krysak

Robert L Bristol

Rami Hourani

Richard E Schenker

Lauren Doyle

Brandon Jay Holybee

Xuanxuan Chen

Kevin Lai Lin

Charles Henry Wallace

Manish Chandhok

Grant M Kloster

Paul Anton Nyhus

Nafees Kabir

Jeffery D Bielefeld

Jessica M Torres

Nityan Labros Nair

Emily Walker

Gauri Nabar

Methods, device structures, and wafer treatment chemistries related to backside wafer treatments to reduce distortions and overlay errors due to wafer deformation during wafer chucking are described. A backside layer is applied to the wafer prior to chucking. The chemistry of the backside layer lowers the surface free energy of the wafer during chucking to eliminate or mitigate wafer deformation during wafer processing.

Backside wafer treatments to reduce distortions and overlay errors during wafer chucking

Described herein are IC devices include tight-pitched patterned metal layers, such as metal gratings, and processes for forming such patterned metal layers. The processes include subtractive metal patterning, where portions of a metal layer are etched and replaced with an insulator to form the metal grating. Masks for etching portions of the metal layer are generated using directed self-assembly (DSA). In some examples, multiple etching steps are performed, e.g., to generate metal lines at a first pitch, and to add additional lines at half of the first pitch. In some examples, additive metal patterning is performed in addition to subtractive metal patterning.

Directed self-assembly enabled subtractive metal patterning

A chemical composition includes a polymer chain having a surface anchoring group at a terminus of the polymer chain. The surface anchoring group is metal or dielectric selective and the polymer chain further includes at least one of a photo-acid generator, quencher, or a catalyst. In some embodiments, the surface anchoring group is metal selective or dielectric selective. In some embodiments, the polymer chain includes side polymer chains where the side polymer chains include polymers of photo-acid generators, quencher, or catalyst.

Chemical compositions and methods of patterning microelectronic device structures

Embodiments herein describe techniques for a semiconductor device including an interconnect structure. The interconnect structure may have a segment of a passivant layer including a SAM. The SAM may include head groups, and chains attached to the head groups. The chains include functional groups that are cross-linkable at end or side of the chains to result in chain extension by reacting with another SAM or polymer, densification by crosslinking with an adjacent SAM, or polymerization having an initiator as the SAM or the SAM attached to another SAM. Other embodiments may be described and/or claimed.

Interconnect structure surface modifications by passivating agents

Disclosed herein are structures and techniques utilizing directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the patterned region.

Directed self-assembly structures and techniques

Multifunctional molecules for selective polymer formation on conductive surfaces, and the resulting structures, are described. In an example, an integrated circuit structure includes a lower metallization layer including alternating metal lines and dielectric lines above the substrate. A molecular brush layer is on the metal lines of the lower metallization layer, the molecular brush layer including multifunctional molecules. A triblock copolymer layer is above the lower metallization layer. The triblock copolymer layer includes a first segregated block component over the dielectric lines of the lower metallization layer, and alternating second and third segregated block components on the molecular brush layer on the metal lines of the lower metallization layer, where the third segregated block component is photosensitive.

Multifunctional molecules for selective polymer formation on conductive surfaces and structures resulting therefrom

Carbon-based dielectric materials for semiconductor structure fabrication, and the resulting structures, are described. In an example, method of patterning a layer for a semiconductor structure includes forming a plurality of trenches in a dielectric layer above a semiconductor layer above a substrate to form a patterned dielectric layer. The method also includes filling the plurality of trenches with an adamantane-based carbon hardmask material. The method also includes removing the patterned dielectric layer selective to the adamantane-based carbon hardmask material. The method also includes using the adamantane-based carbon hardmask material to pattern the semiconductor layer.

Carbon-based dielectric materials for semiconductor structure fabrication and the resulting structures

In an example, there is disclosed an integrated circuit, having: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; and an etch-resistant plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect.

Hardened plug for improved shorting margin

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Hillsboro, OR, United States of America

Tayseer Mahdi