Realtek Semiconductor Inc.

Tay-Her Tsaur

Po-Ching Lin

Cheng-Cheng Yen

Hsin-Cheng Hsu

Ta-Hsun Yeh

Chien-Ming Wu

Chung-Yu Huang

Shih-Hsin Liao

Jyun-Ren Chen

Chien Ming Wu

Chao-Cheng Lee

Chen-Chih Huang

Tzu-Chien Tzeng

Tsung-Yen Tsai

Jian Liu

Ming-Yuh Yeh

Cheng-Pang Chan

Chih-Fu Tsai

An integrated circuit includes a load circuit and an electrostatic discharge (ESD) circuit. The load circuit includes a first and a second I/O terminal. The ESD circuit is coupled to the first and the second I/O terminal. The ESD circuit includes a first protection circuit configured to conduct a first ESD current from the first to the second I/O terminal. The first protection circuit includes a first, a second, a third doped region, and a well. The first doped region is coupled to the first I/O terminal, and has a first conductive type. The well is coupled to the first doped region, and has a second conductive type different from the first conductive type. The second doped region is coupled to the well, and has the first conductive type. The third doped region couples the second doped region to the second I/O terminal, and has the second conductive type.

Integrated circuit and electrostatic discharge protection method

The present invention discloses an electrostatic discharge protection circuit having time-extended discharging mechanism. A RC circuit is coupled between an ESD input terminal that receives an ESD input and a ground terminal and includes an input control terminal. An inverter includes a P-type transistor coupled between the ESD input terminal and an output control terminal and an N-type transistor circuit including N-type transistors coupled in series and between the output control terminal and a ground terminal, wherein two of the N-type transistors has an internal connection terminal. Gates of the P-type transistor and N-type transistors are controlled by the input control terminal. A switch transistor is coupled between the ESD input terminal and the internal connection terminal. A discharging transistor is coupled between the ESD input terminal and the ground terminal. The gates of the switch transistor and the discharging transistor are controlled by the output control terminal.

Electrostatic discharge protection circuit having time-extended discharging mechanism

An electrostatic discharge protection circuit includes a voltage drop circuit, a detector circuit, and a clamping circuit. The voltage drop circuit is configured to generate a second voltage according to a first voltage. The second voltage is smaller than the first voltage. The detector circuit is coupled to the voltage drop circuit. The detector circuit is configured to generate a control signal according to the second voltage and an input voltage. The clamping circuit is coupled to the voltage drop circuit and the detector circuit. The clamping circuit is configured to provide an electrostatic discharge path according to a voltage level of the control signal.

Electrostatic discharge protection circuit and operation method

The present invention discloses an electrostatic discharge protection circuit having false-trigger prevention mechanism. A RC circuit, including an input control terminal, is coupled between an electrostatic discharge input terminal for receiving an input power and a ground terminal. An inverter includes a P-type transistor circuit, including P-type transistors coupled between the electrostatic discharge input terminal and an output control terminal in series and having an internal connection terminal between two of the P-type transistors, and an N-type transistor, coupled between the output control terminal and the ground terminal. Gates of the P-type and N-type transistors are controlled by the input control terminal A switch transistor, having the gate controlled by the input control terminal, is coupled between the internal connection terminal and the ground terminal. A discharging transistor having the gate controlled by the output control terminal, is coupled between the electrostatic discharge input terminal and the ground terminal.

Electrostatic discharge protection circuit having false-trigger prevention mechanism

A semiconductor device includes an active area structure, at least one gate and at least one isolation structure. The active area structure is arranged along a first direction. The at least one gate is arranged above the active area structure and along a second direction. The second direction is different from the first direction. The at least one isolation structure is arranged in the active area structure. A length of the at least one isolation structure is shorter than a width of the active area structure in the second direction.

Semiconductor device

The present disclosure discloses an output circuit having a voltage-withstanding mechanism that includes a PMOS, a NMOS, a voltage-withstanding auxiliary NMOS and a voltage-withstanding auxiliary circuit. The PMOS includes a first source terminal and a first drain terminal coupled to a voltage source and an output terminal and a first gate receiving a first input signal. The NMOS includes a second source terminal and a second drain terminal coupled to a ground terminal and a connection terminal and a second gate receiving a second input signal. The auxiliary NMOS includes a third drain terminal and a third source terminal coupled to the output terminal and the connection terminal. The auxiliary circuit is coupled to the voltage source and a third gate of the auxiliary NMOS and provides a current conducting mechanism and a resistive mechanism respectively when the output terminal is operated at a logic high level and a logic low level.

Output circuit having voltage-withstanding mechanism

An electrostatic discharge (ESD) protection device includes a voltage divider circuit, a detection circuit, and a clamping circuit. The voltage divider circuit outputs N&#x2212;1 bias voltages according to a first voltage and a second voltage, in which N is a positive integer greater than or equal to 2. The detection circuit detects an ESD event according to a voltage level at a predetermined node associated with the first voltage and the second voltage, and to generate N control signals according to the first voltage, the second voltage, and the N&#x2212;1 bias voltages. When the ESD event occurs, the voltage level of the N control signals are the same as the first voltage. The clamping circuit is turned on according to the N control signals when the ESD event occurs, in order to provide a discharging path of a current associated with the ESD event.

Electrostatic discharge protection device and electrostatic discharge detector circuit

Disclosed is a transmission gate circuit including a control voltage generating circuit, a high voltage transmission circuit and a low voltage transmission circuit. The high and low voltage transmission circuits are coupled between an input terminal and an output terminal. The control voltage generating circuit generates two voltage groups according to an input voltage of the input terminal and an enable voltage and thereby controls the high and low voltage transmission circuits with the two voltage groups respectively. When the enable voltage is high, one voltage group includes identical voltages while a difference between any of the identical voltages and any voltage of the other voltage group is not higher than a predetermined voltage; when the enable voltage is low, each voltage group includes decremental voltages. The high/low voltage transmission circuit is turned on when the enable voltage is high and the input voltage is high/low.

Transmission gate circuit

Disclosed is an inverter capable of withstanding a high voltage. The inverter includes a control voltage generating circuit, a high voltage transmission circuit, and a low voltage transmission circuit. The control voltage generating circuit generates a first group of control voltages and a second group of control voltages according to an input voltage, in which one group includes decrement voltages and the other group includes identical voltages. The high/low voltage transmission circuit is coupled between a high/low voltage terminal and an output terminal, wherein when the input voltage is low/high, the high/low voltage transmission circuit is turned on according to the first/second group of control voltages so that an output voltage of the output terminal is equal to a high/low voltage of the high/low voltage terminal.

Inverter with control voltage generating circuit capable of withstanding high voltage

An ESD protection device includes a detection circuit and a clamping circuit. The detection circuit is configured to output a first control signal and a second control signal according to a first voltage and a second voltage that is different from the first voltage, in which if an ESD event occurs, the detection circuit is configured to perform an inverse operation according to the second voltage, in order to generate the first control signal and the second control signal. The clamping circuit is configured to be turned on according to the first control signal and the second control signal, in order to provide a discharging path for a current associated with the ESD event.

Electrostatic discharge protection device, detection circuit and protection method thereof

A voltage level shifter circuit, including: a first control circuit, arranged to receive an input voltage and generate a first control signal; a first pull-down circuit, arranged to determine whether to pull down a first output voltage to a first reference voltage according to the first control signal; a first pull-up circuit, arranged to determine whether to pull up the first output voltage to a second reference according to a first inverse output voltage; a second control circuit, arranged to generate a second control signal according to the first output voltage; a second pull-down circuit, arranged to determine whether to pull down a second output voltage to the second reference voltage according to the second control signal; and a second pull-up circuit, arranged to determine whether to pull up the second output voltage to a third reference voltage according to a second inverse output voltage.

Voltage level shifter circuit

This disclosure provides an ESD protection circuit coupled to a first and a second terminals of a differential-pair circuit. The ESD protection circuit includes: an ESD sensing unit coupled to the first and the second terminals and sensing electrical changes at the first and the second terminals to generate a first trigger signal; and a first discharging unit coupled to the ESD sensing unit and turning on a first discharging path according to the first trigger signal.

Electro-static discharge protection circuit

The present invention discloses a buffer circuit including: a pre-driver providing a first, a second, a third and a fourth driving signals according to the voltages of voltage nodes and control signals; a voltage-detection and bias circuit providing bias voltages for an output buffer and an input buffer according to the voltages of the voltage nodes and the third driving signal; the output buffer determining conduction states of the transistors of the output buffer according to the voltages of the voltage nodes, the first and the second driving signals, and the bias voltages, and thereby outputting an output signal to a signal pad; and the input buffer determining the conduction states of the transistors of the input buffer according to the voltage of the signal pad, the voltages of the voltage nodes, the fourth driving signals, and the several bias voltages, and thereby generating an input signal.

Buffer circuit

An ESD protection circuit includes: a first current path switch arranged in a parallel connection with a first circuit and turned off when a first node voltage is at a logic low level; a first node for providing the first node voltage; a resister element coupled between a first power terminal and the first node; a MOS capacitor coupled between the first node and a first fixed-voltage terminal; a second current path switch arranged in a parallel connection with a second circuit and controlled by a second node voltage; a switch control circuit for providing the second node voltage; and a node voltage control circuit for controlling the first node voltage according to the second node voltage to ensure the first current path switch is turned off when the first power terminal supplies power to the first circuit while the second power terminal supplies power to the second circuit.

Cross-domain ESD protection circuit

An ESD protection circuit includes: a first current path switch arranged in a parallel connection with a first circuit and turned off when a first node voltage is at a logic high level; a first node for providing the first node voltage; a resister element coupled between a first power terminal and the first node; a MOS capacitor coupled between the first node and a first fixed-voltage terminal; a second current path switch arranged in a parallel connection with a second circuit and controlled by a second node voltage; a switch control circuit for providing the second node voltage; and a node voltage control circuit for controlling the first node voltage according to the second node voltage to ensure the first current path switch is turned off when the first power terminal supplies power to the first circuit while the second power terminal supplies power to the second circuit.

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Tai-Nan, Taiwan

Tay-Her Tsaur