Telefonaktiebolaget Lm Ericsson (Publ)

Tawfik Lazraq

Farooq U Khan

Hannu Tenhunen

Mehran Mikhtari

P Bergstedt

An algorithm complementary to the Selective Repeat ARQ technique is provided, that allows obsolete or otherwise superfluous packets to be safely discarded at the transmitter when using the Selective Repeat ARQ technique. Thus, clogging of ARQ buffers and deadlocking of the system can be avoided, and data transfer in mobile wireless environments using Selective Repeat ARQ can be made more efficient. In accordance with various embodiments of the algorithm, a data packet discard notification (DPDN) message is sent by the transmitter to the receiver to indicate to the receiver which packets the transmitter has discarded, so that the receiver need no longer expect to receive them. The DPDN message can be sent when the transmitter discards packets. The DPDN message can also be sent in response to a communication such as a request or negative acknowledgment that is sent by the receiver to the transmitter.

Data packet discard notification

An ATM-switch for high transmission rates is built of primary switch cores. A path for a cell through the switch is determined at the arrival of the cell at the switch and this path is coded as a control word, which is transferred through the switch in parallel to the cell itself. The control word indicates directly how the transfer through each primary element of the switch is to be made. Each primary element must only have two inputs and two outputs. The control word then consists of one bit for every stage of primary switch elements in the switch and this bit indicates directly the output from which the cell is to be forwarded from a considered switch element. The switch cores are constructed of intermediate storage memories, one for each pair of one input and one output, and these intermediate storage memories can have a rather limited capacity for storing only a few cells together with their associated control words. The control word indicates to a cell arriving at an input the intermediate storage memory, where the cell is to be intermediately stored. The intermediate storage memories can be shift registers and independent units take care of the storing of cells and the forwarding of cells from the switch core.

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Lidingö, Sweden

Tawfik Lazraq