Intel Corporation

Tatyana N Andryushchenko

Aleksandar Aleksov

Mauro J Kobrinsky

Anne E Miller

David W Staines

Patrick R Morrow

Qing Ma

Paul B Fischer

Rajendra C Dias

Jun He

Sridhar Balakrishnan

Guanghai Xu

Satish Radhakrishnan

Srinivas V Pietambaram

Hui Jae Yoo

Dilan Seneviratne

Javier Soto Gonzalez

Ramanan Chebiam

Manish Dubey

Alejandro X Levander

Rafiqul Islam

Embodiments of the invention include a microelectronic device and methods for forming a microelectronic device. In an embodiment, the microelectronic device includes a semiconductor die that has one or more die contacts that are each electrically coupled to a contact pad by a conductive trace. The semiconductor die may have a first elastic modulus. The microelectronic device may also include an encapsulation layer over the semiconductor die and the conductive trace. The encapsulation layer may have a second elastic modulus that is less than the first elastic modulus. The microelectronic device may also include a first strain redistribution layer within the encapsulation layer. The first strain redistribution layer may have a footprint that covers the semiconductor die and a portion of the conductive traces. The strain redistribution layer may have a third elastic modulus that is less than the first elastic modulus and greater than the second elastic modulus.

Stretchable electronics fabrication method with strain redistribution layer

Generally discussed herein are systems and methods that can include a stretchable and bendable device. According to an example a method can include (1) depositing a first elastomer material on a panel, (2) laminating trace material on the elastomer material, (3) processing the trace material to pattern the trace material into one or more traces and one or more bond pads, (4) attaching a die to the one or more bond pads, or (5) depositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials.

Bendable and stretchable electronic devices and methods

In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for gradient encapsulant protection of devices in stretchable electronic. For instance, in accordance with one embodiment, there is an apparatus with an electrical device on a stretchable substrate; one or more stretchable electrical interconnects coupled with the electrical device; one or more electrical components electrically coupled with the electrical device via the one or more stretchable electrical interconnects; and a gradient encapsulating material layered over and fully surrounding the electrical device and at least a portion of the one or more stretchable electrical interconnects coupled thereto, in which the gradient encapsulating material has an elastic modulus greater than the stretchable substrate and in which the elastic modulus of the gradient encapsulating material is less than the electrical device. Other related embodiments are disclosed.

Gradient encapsulant protection of devices in stretchable electronics

The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.

Debond interconnect structures

Interconnect structures including a selective via post disposed on a top surface of a lower level interconnect feature, and fabrication techniques to selectively form such a post. Following embodiments herein, a minimum interconnect line spacing may be maintained independent of registration error in a via opening. In embodiments, a selective via post has a bottom lateral dimension smaller than that of a via opening within which the post is disposed. Formation of a conductive via post may be preferential to a top surface of the lower interconnect feature exposed by the via opening. A subsequently deposited dielectric material backfills portions of a via opening extending beyond the interconnect feature where no conductive via post was formed. An upper level interconnect feature is landed on the selective via post to electrically interconnect with the lower level feature.

Scalable interconnect structures with selective via posts

Methods of fabricating an interconnect, which fundamentally comprises forming a second conductive film (e.g., aluminum) over first conductive film (e.g., copper) deposited in an opening formed in a dielectric layer (e.g., low-k dielectric). The second conductive film has an ability to reflow to form a planar surface upon a thermal treatment process. Electropolishing is then used to planarize the second and first conductive films, wherein an electrolyte solution selective to remove the first conductive film faster than the second conductive film is used. An interconnect is formed.

Method for forming planarizing copper in a low-k dielectric

A method of forming a metal interconnect for an integrated circuit includes depositing a barrier layer on a dielectric layer having a trench formed therein, depositing an adhesion layer on the barrier layer, depositing a metal layer on the adhesion layer, removing the metal layer using a CMP process until at least a portion of the adhesion layer is exposed, and removing portions of the adhesion layer and the barrier layer sited substantially outside of the trench using a dissolution process. The dissolution process applies an electrolyte solution to those portions of the adhesion layer and the barrier layer sited substantially outside of the trench to dissolve and remove them.

Chemical dissolution of barrier and adhesion layers

The present application discloses process comprising providing a wafer, the wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD, and a barrier layer deposited on the under-layer, and a conductive layer deposited in the feature, placing the wafer in an electrolyte, such that at least the barrier layer is immersed in the electrolyte, and applying an electrical potential between the electrode and the wafer. Also disclosed is an apparatus comprising a vessel having an electrolyte therein, a first electrode at least partially immersed in the electrolyte, the first electrode comprising a wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD layer, a barrier layer deposited on the under-layer and a conductive layer deposited in the feature, a second electrode at least partially immersed in the electrolyte, and a potential source for applying a potential difference between the first and second electrodes. Other embodiments are also disclosed and claimed.

Damascene fabrication with electrochemical layer removal

A copper damascene process for a mechanically weak low k dielectric layer is described. Electropolishing is used to etch back the copper. A sacrificial conductive layer beneath the barrier layer assures complete planarization of the copper.

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Beaverton, OR, United States of America

Tatyana N Andryushchenko