Cadence Design Systems, Inc.

Synopsys, Inc.

Tatung Chow

Abdurrahman Sezginer

Thomas Christopher Cecil

Hsu-Ting Huang

Gokhan Percin

Changqing Hu

Jesus Orsely Carrero

Kostyantyn Chuyeshov

Donghwan Son

David H Kim

During a calculation technique, at least a portion of a target pattern associated with an integrated-circuit design is modified so that polygons in the target pattern, which represent features in the design, result in acceptable accuracy during a photolithographic process that fabricates the target pattern on a semiconductor die. In particular, a set of polygon parameters associated with the polygons are modified, as needed, so that a cost function that corresponds to a difference between a modified target pattern and an estimated target pattern produced during the photolithographic process meets a termination criterion. A mask pattern that can fabricate the modified target pattern on the semiconductor die is calculated using an inverse optical calculation in which the modified target pattern is at an image plane of an optical path associated with the photolithographic process and the mask pattern is at an object plane of the optical path.

Lithographically enhanced edge determination

The present invention provides a method for calibrating a computational model of a lithography process by calculating a demerit function using an intensity measurement at a location of a wafer; and calibrating the lithography model or a mask making model by determining values of parameters of the computational model using the calculated demerit function. The method may also use a second demerit function that is defined by the sum of squares of differences between a simulated and measured critical dimensions of a feature on the wafer.

System and method for calibrating a lithography model

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San Jose, CA, United States of America

Tatung Chow