The Furukawa Electric Co., Ltd.

Fuji Electric Co., Ltd.

Tatsuyuki Shinagawa

Noriyuki Yokouchi

Norihiro Iwai

Kazuyuki Umeno

Akihiko Kasukawa

Keishi Takaki

Hirotatsu Ishii

Ryosuke Tamura

Shinya Ootomo

Natsumi Ueda

Sadahiro Kato

Seikoh Yoshida

Takehiko Nomura

Masayuki Iwami

Hiroshi Kambayashi

Jiang Li

Yuki Niiyama

Takuya Kokawa

Ryohei Makino

Masato Tachibana

A semiconductor multi-layer substrate includes a substrate made of Si and a multi-layer semiconductor layer. The multi-layer semiconductor layer includes an active layer made of a nitride semiconductor, a first warp control layer being formed between the substrate and the active layer and giving a predetermined warp to the substrate, and a second warp control layer made of a nitride semiconductor of which amount of an increase in a warp per a unit thickness is smaller than an amount of increase in the warp per a unit thickness of the first warp control layer. A total thickness of the multi-layer semiconductor layer is equal to or larger than 4 &#x3bc;m.

Semiconductor multi-layer substrate, semiconductor device, and method for manufacturing the same

A semiconductor multi-layer substrate includes a substrate, a buffer layer formed on the substrate and made of a nitride semiconductor, an electric-field control layer formed on the buffer layer and made of a nitride semiconductor, the electric-field control layer having conductivity in the substrate's lateral direction, an electric-field relaxation layer formed on the electric-field control layer and made of a nitride semiconductor, and an active layer formed on the electric-field relaxation layer and made of an nitride semiconductor. A resistance in the substrate's lateral direction of the electric-field control layer is equal to or smaller than 10 times a resistance of the electric-field relaxation layer, and a ratio of an electric field share between the electric-field relaxation layer and the buffer layer is controlled by a ratio between a thickness of the electric-field relaxation layer and a thickness of the buffer layer.

Semiconductor multi-layer substrate and semiconductor element

A nitride compound semiconductor device includes: a substrate; a buffer layer formed on the substrate and including a plurality of composite layers each layered of: a first layer formed of a nitride compound semiconductor; and a second layer formed of a nitride compound semiconductor containing aluminum and having a lattice constant smaller than a lattice constant of the first layer; a semiconductor operating layer formed on the buffer layer; and a plurality of electrodes formed on the semiconductor operating layer. At least one of the second layers has oxygen added therein.

Nitride compound semiconductor device and manufacturing method thereof

An interfacial reaction suppressing layerformed between an oxide layer including a ZnO single crystal substrateand a nitride layer including an InGaN semiconductor layerrestrains the interfacial reaction between the oxide layer and the nitride layer and formation of a reaction layer (AlZnO) at the interface, which makes it possible to grow and thermally treat the InGaN semiconductor layerat a high temperature. Thus, a crystal quality of the InGaN semiconductor layeris improved.

Nitride based semiconductor device and method of manufacturing the same

A semiconductor light emitting element of the present invention comprises: a zinc oxide (ZnO) single crystal substratewith a substrate surface of a plane orientation insusceptible to a piezo electric field; a Lattice-matched layerformed on the substrate surface to be lattice-matched with the ZnO single crystal substrate; an active layerof indium gallium nitride (InGaN, 0&#x3c;x&#x3c;1); two of cladding layersandto be lattice-matched with the active layerand/or the Lattice-matched layer

Semiconductor light emitting element and method of manufacturing therefor

Provided is a normally-off field effect transistor using a III-nitride semiconductor. The transistor is provided with a III-nitride semiconductor layer grown on a substrate by including an acceptor and a donor; a gate insulating film which is formed on the III-nitride semiconductor layer to have a thickness to be at a prescribed threshold voltage based on the concentration of the acceptor and that of the donor; a gate electrode formed on the gate insulating film; a first source/drain electrode formed on the III-nitride semiconductor layer to one side of and separate from the gate electrode, directly or via a high dopant concentration region; and a second source/drain electrode formed away from the gate electrode and the first source/drain electrode, on or under the III-nitride semiconductor layer, directly or via a high dopant concentration region.

Normally-off field effect transistor using III-nitride semiconductor and method for manufacturing such transistor

A surface emitting semiconductor laser device including a substrate, a bottom DBR, and a mesa post having a layer structure, the layer structure including a top DBR including a plurality of pairs, each of said pairs including an Al-containing high-reflectivity layer and an Al-containing low-reflectivity layer, an active layer structure sandwiched between the DBRs for emitting laser, and a current confinement layer disposed within or in a vicinity of one of the DBRs, the current confinement layer including a central current injection area and an annular current blocking area encircling the central current injection area, the annular current blocking area being formed by selective oxidation of Al in an AlGaAs layer (0.95&#x2266;x&#x3c;1) having a thickness below 60 nm, the Al-containing low-reflectivity layer including Al at an atomic ratio not more than 0.8 and below 0.9. The progress of the oxidation in the Al-containing compound semiconductor layers can be suppressed during the formation of the current confinement oxide area by restricting the Al content in the specified range, thereby realizing the surface emitting semiconductor laser device having the longer lifetime, or the higher reliability.

Surface emitting semiconductor laser device

A vertical cavity surface emitting semiconductor laser (VCSEL) device has p-type and n-type DBRs sandwiching therebetween a resonant cavity including an active layer. Each the DBRs has a plurality of layer pairs each including a AlGaAs high-reflectivity layer and an AlGaAs low-reflectivity layer and an AlGaAs slope content layer interposed between each of the high-reflectivity layers and adjacent low-reflectivity layer. The slope content layers in the vicinity of the active layer has an Al content x3 wherein 0&#x3c;x3&#x2266;0.3 and 0.55&#x2266;x3&#x3c;1 and an impurity concentration of 3&#xd7;10cmor above.

Vertical cavity surface emitting semiconductor laser device

A surface emitting semiconductor laser device of oxidized-Al current confinement structure has a resonant wavelength of a fundamental transverse mode, which is set shorter than or equal to a peak-gain wavelength of the laser device at a specified temperature. The surface emitting semiconductor laser device emits in a single-transverse mode.

A vertical cavity surface emitting laser (VCSEL) device includes a pair of diffusion Bragg reflectors (DBRs) sandwiching therebetween a multiple quantum well (MQW) comprising active layers. The bottom DBR includes a lower layer structure having AlAs layers having a higher thermal conductivity and AlGaAs layers in pair and an upper layer structure acting anti-oxidation layers and having a pair of AlGaAs layers having different Al contents. A selectively oxidized AlAs layer disposed as the top layer of the bottom DBR comprises an Al-oxidized area and a non-oxidized layer for confinement of current injection path.

Vertical cavity surface emitting laser device

A semiconductor device including a substrate, a mesa post overlying the substrate and having a substantially cylindrical shape, a resin member surrounding the mesa post and a stress moderating member received in the mesa post for moderating stress between the mesa post and the resin member. The stress applied to the mesa post is reduced because the entire volume of the resin member is divided by the stress moderating member and each of the divided resin members reduces the stress.

Growing community of inventors

Tokyo, Japan

Tatsuyuki Shinagawa