Fujitsu Corporation

Ramtron International Corporation

Tatsuya Yamazaki

Kenichi Goto

Atsuo Fushida

Hisashi Miyazawa

Kenichi Inoue

Hideo Takagi

Yuzuru Ota

Keisuke Okazaki

Shinichi Kawai

Takae Sukegawa

Hiromi Hayashi

George Argos, Jr

Tetsuo Izawa

Masataka Kase

Takashi Sakuma

Masaki Katsube

Keng Tan

A method of manufacturing a semiconductor device which has the steps of: forming an insulated gate field effect transistor of a first conductivity type on a semiconductor substrate; forming a first insulating film over the semiconductor substrate, the first insulating film covering the insulated gate electrode; forming a contact window through the first insulating film to at least one of the source/drain regions; embedding a metal plug in the contact window; forming a second insulating film having an oxygen blocking function on the first insulating film, the second insulating film covering the metal plug; forming a capacitor lower electrode on the second insulating film; forming a dielectric oxide film having a perovskite crystal structure on the lower electrode; annealing the semiconductor substrate in an oxygen-containing atmosphere; and forming a capacitor upper electrode on the dielectric oxide film. A semiconductor device can be realized which has capacitors with dielectric oxide films of a perovskite crystal structure having a high dielectric constant.

Semiconductor device with perovskite capacitor and its manufacture method

A method of manufacturing a semiconductor device with a silicide electrode is provided which can form a good contact even at a scaled-down pattern. The method includes the steps of: forming an insulated gate structure with side wall spacer on a p-type region of a silicon (Si) substrate; implanting arsenic ions in source/drain regions at a dose less than 5&times;10,cm,; forming a laminated layer of a Co film and a TiN film on the surface of the substrate; heating the substrate to let the Co film react with an underlying Si region for silicidation; and removing the TiN film. Another method includes the steps of: forming a field oxide film on the surface of a silicon (Si) substrate for element isolation; implanting ions in the surface region of the Si substrate defined by the field oxide film to form a conductive silicon region; depositing a Co film on the Si surface extending to the field oxide film; heating the Si substrate under such conditions of a time and a temperature that does not allow CoSi,to be formed, and lets the Co film react with the conductive silicon region for silicidation, thereby forming Co silicide; removing an unreacted Co film; and subjecting the Si substrate to another heat treatment to convert the Co silicide to CoSi,.

Manufacture of semiconductor device with salicide electrode

A semiconductor device is produced by a method which comprises forming a conductor pattern in or on a semiconductor layer, covering the surface of the conductor pattern with an antioxidant conductor layer, forming a first insulating layer on the semiconductor layer, forming a lower electrode of a capacitor on the first insulating layer, forming a dielectric layer of an oxygen-containing material on the lower electrode, forming an upper electrode on the dielectric layer, sequentially patterning the upper electrode, the dielectric layer, and the lower electrode in the shape of a capacitor, forming a second insulating layer covering the semiconductor layer, the antioxidant conductor layer, and the capacitor, patterning the second insulating layer thereby simultaneously forming a first opening and a second opening on the upper electrode and the conductor pattern, heating the interiors of the first opening and the second opening and the upper electrode in an oxygen-containing atmosphere, forming a conductor layer overlying the second insulating layer and filling the interiors of the first and second openings, and patterning the conductor layer thereby forming a first wiring connected to the upper electrode through the first opening and a second wiring electrically continuing to the conductor pattern through the second opening.

Method for production of semiconductor device

A manufacturing method of a semiconductor device of the present invention comprises the steps of forming an amorphous layer on an upper layer of the impurity diffusion layer made of silicon by virtue of ion-implantation, forming a cobalt film on the impurity diffusion layer, forming a cobalt silicide layer made of Co.sub.2 Si or CoSi on an upper layer of the amorphous layer at a low temperature by reacting the cobalt film to silicon in the impurity diffusion layer in virtue of first annealing, then removing the cobalt film which has not reacted, and changing Co.sub.2 Si or CoSi constituting the cobalt silicide layer into CoSi.sub.2 to have low resistance and also rendering the cobalt silicide layer to enter into a depth identical to or deeper than an initial depth of the amorphous layer in virtue of second annealing.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device which has the steps of: forming an insulated gate field effect transistor of a first conductivity type on a semiconductor substrate,; forming a first insulating film over the semiconductor substrate, the first insulating film covering the insulated gate electrode; forming a contact window through the first insulating film to at least one of the source/drain regions; embedding a metal plug in the contact window; forming a second insulating film having an oxygen blocking function on the first insulating film, the second insulating film covering the metal plug; forming a capacitor lower electrode on the second insulating film; forming a dielectric oxide film having a perovskite crystal structure on the lower electrode; annealing the semiconductor substrate in an oxygen-containing atmosphere; and forming a capacitor upper electrode on the dielectric oxide film. A semiconductor device can be realized which has capacitors with dielectric oxide films of a perovskite crystal structure having a high dielectric constant.

A dual-level metalization method for ferroelectric integrated circuits includes the steps forming a planarized oxide layer over a partially formed integrated circuit ferroelectric device, forming a cap layer over the planarized oxide layer, forming vias into the planarized oxide layer and cap layer to provide access to the desired first-level metal contacts, and metalizing the selected first-level metal contacts with second-level metal. The cap layer can be doped or undoped titanates, zirconates, niobates, tantalates, stanates, hafnates, or manganates such as doped and undoped PZT (lead zirconate titanate), BST (barium strontium titanate), or SBT (strontium bismuth tantalate).

Dual-level metalization method for integrated circuit ferroelectric

On a semiconductor substrate with an exposed silicon region, a metal layer such as Co is deposited and a silicide layer is formed by heat treatment. Thereafter, a metal layer such as Ni and a silicon layer are deposited, and one of them is patterned. The metal layer and silicon layer are heated for silicification to form a local interconnect. A semiconductor device manufacturing method is provided which uses salicide technique and can form a local interconnect of good quality.

Method of making a semiconductor device having a silicide local

A semiconductor device includes an insulating support layer on which are mounted, in succession, a conductive layer, a buried layer comprising first and second spaced portions and a semiconductor single crystal layer comprising spaced first and second portions respectively supported on the first and second spaced portions of the buried layer, the respective first and second portions having respective, first and second common sidewalls defining respective, first and second peripheries thereof and respectively comprising a transistor region and a collector electrode region. A remaining exposed surface portion of the conductive layer extends between the spaced, opposing portions of the sidewalls of the transistor and collector electrode regions. An insulating material layer is supported on the first portion remaining exposed surface portion of the conductive layer and extending between and engaging the spaced and opposed portions of the peripheral sidewalls of the transistor and collector electrode regions, and a second portion engaging and extending from the remaining portions of the peripheral sidewalls of the transistor and collector electrode regions. The conductive layer electrically couples the transistor region and the collector electrode region and further comprises an electrical interconnection layer.

Growing community of inventors

Kawasaki, Japan

Tatsuya Yamazaki