Mitsubishi Denki Kabushiki Kaisha

Sumitomo Precision Products Co., Ltd.

Renesas Technology Corp.

Tatsuya Ueda

Toyohiko Yoshida

Toru Kengaku

Tomohiro Sakurai

Sachio Nagamitsu

Hiromasa Hayashi

A heat exchanger () for an aircraft engine includes a core () and radiating fins (). The radiating fins are configured such that a ratio y/Y of a height y from a surface () of the core to a formation position of a connecting portion () to a total height Y of each of the radiating fins () from the surface of the core satisfies a relationship of 0.34<y/Y<0.64.

Heat exchanger for aircraft engine

A heat exchanger for an aircraft engine that allows improvement in heat exchange ratio is provided. The heat exchanger () includes a plurality of heat dissipating fins (). The plurality of heat dissipating fins () are arranged on at least one of a surface () and a surface (). Each of the heat dissipating fins () has a plate-like shape and has an inlet-side upper edge disposed on the side where a swirl flow (AF) flows in and an outlet-side upper edge disposed on the side opposite the inlet-side upper edge and on the side where the swirl flow (AF) flows out, and the inlet-side upper edge intersects the axis of rotation of a fan and extends along the direction in which the swirl flow (AF) flows at the inlet-side upper edge.

A heat exchanger for an aircraft engine includes: a body including a plate-like first member and a plate-like second member that are stacked in a thickness direction of the first and second members and joined together, and a channel which is defined in the body and in which the cooling target fluid flows; and a corrugated fin plate disposed in the channel in the body. The body is bent along a curved surface to which the heat exchanger is attached. A plurality of heat dissipation fins stand on an outer surface of at least one of the first member or the second member.

When a line number counted by a line number counting unit corresponds to a prescribed line number, a transfer source address generating unit adds an offset address set in an offset address setting unit to respective transfer source addresses to output as addresses to a memory. A DMA control unit controls DMA transfer in accordance with a transfer source address generated by the transfer source address generating unit and a transfer destination address generated by a transfer destination address generating unit. Thus, rapid enlargement/reduction of image data becomes possible.

Image data enlarging/reducing apparatus enlarging/reducing image data by direct memory access transfer

The data processor related to the invention enables to designate whether the branch prediction mechanism itself should be activated or not for a conditional branch instruction, and the data processor enables to initialize branch history as required and also designates activation or inactivation of the branch prediction mechanism by setting a specific value to a specific bit of an exclusive usable register by software means. Also when a specific instruction is executed, the data processor automatically clears the branch history. As a result, in the event when the data processing efficiency is adversely declined by application of branch prediction mechanism or when monitoring external address bus, the branching prediction mechanism can be inactivated by setting the predetermined value to the exclusive usable register. Likewise, when the reliability of the branch history lowers due to such as variation in the program running condition, the data processor is capable of clearing the branch history by writing a specific value into the exclusive usable register, and when executing a specific instruction which varies the program executing condition, branch history is automatically cleared.

Data processor with selectively enabled and disabled branch prediction

A pipelined multi-stage data processor has a bypass circuit which is enabled when a memory reading request signal from the operand fetch stage and a memory writing request signal from the execution stage are simultaneously received by a control device with respect to an identical location in the memory. The bypass circuit operates to cause the write data to be written into the memory to be directly transferred to the fetch stage so that the memory reading operation is performed without actually accessing the memory.

Pipelined multi-stage data processor including an operand bypass

Conventional microprocessors access cache memory and external memory using a common data bus and share a single program counter. According to this invention, the cache memory and the external memory have corresponding program counters and separate data buses. The capacity to update the cache memory program counter concurrently with a cache memory access increases the speed of data processing.

Data processor with instruction cache memory

When a carry signal generated in an n-th bit is propagated to an (n+1)th bit, two n-MOS transistors (12.sub.n+1 and 13.sub.n+1) connected by a signal line (C.sub.n) are turned on to prompt transition of the signal line (C.sub.n) to a zero potential, thereby to increase the speed for propagating the carry signal. When the signal line (C.sub.n) propagates no carry signal, a p-MOS transistor (11.sub.n+1) is turned on to pull up the signal line (C.sub.n) to a supply potential V.sub.CC, thereby to stabilize the potential thereof.

Growing community of inventors

Hyogo, Japan

Tatsuya Ueda