Sumitomo Electric Industries, Limited

Tatsuya Tanabe

Shin Hashimoto

Makoto Kiyama

Takashi Sakurada

Kouhei Miura

Katsushi Akita

Hideaki Nakahata

Hiroshi Amano

Tomihito Miyazaki

Youichi Nagai

So Tanaka

Takashi Ishizuka

Kei Fujii

Akihiro Moto

Nobuyuki Ikoma

A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of AlGaN (0&#x3c;X&#x2266;1), a first AlGaN layer made of group III nitride-based semiconductor containing Al and disposed on the substrate, and a second AlGaN layer made of group III nitride-based semiconductor having a bandgap greater than the first AlGaN layer and disposed thereon. The full width at half maximum values of X-ray rocking curves for (0002) and (10-12) planes of the first AlGaN layer are less than 1000 arcseconds.

Group III nitride semiconductor wafer and group III nitride semiconductor device

In a group III nitride hetero junction transistor, a second AlInGaN layerforms a hetero junctionwith a first AlInGaN layer. A first electrodeforms a Schottky junction with the first AlInGaN layer. The first AlInGaN layerand the second AlInGaN layerare provided over a substrate. The electrodes, andinclude a source electrode, a gate electrode, and a drain electrode, respectively. The carbon concentration NC13 in the first AlInGaN layeris less than 1&#xd7;10cm. The dislocation density D in the second AlInGaN layeris 1&#xd7;10cm. The hetero junctiongenerates a two-dimensional electron gas layer. These provide a low-loss gallium nitride based electronic device.

III nitride electronic device and III nitride semiconductor epitaxial substrate

A method for manufacturing a semiconductor device, by which a multiple quantum well structure having a large number of pairs can be efficiently grown while maintaining good crystalline quality, and the semiconductor device, are provided. The semiconductor device manufacturing method of the present invention includes a step of forming a multiple quantum well structurehaving 50 or more pairs of group III-V compound semiconductor quantum wells. In the step of forming the multiple quantum well structure, the multiple quantum well structure is formed by metal-organic vapor phase epitaxy using only metal-organic sources (all metal-organic source MOVPE).

Semiconductor device and manufacturing method thereof

Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be reduced. In a high electron mobility transistor, a supporting substrateis composed of AlN, AlGaN, or GaN, specifically. An AlGaN epitaxial layerhas a full-width-at-half maximum of (0002) plane XRD of 150 sec or less. A GaN epitaxial layeris provided between the gallium nitride supporting substrate and the AlGaN epitaxial layer (0&#x3c;Y&#x2266;1). A Schottky electrodeis provided on the AlGaN epitaxial layer. The Schottky electrodeconstitutes a gate electrode of the high electron mobility transistor. The source electrodeis provided on the gallium nitride epitaxial layer. The drain electrodeis provided on the gallium nitride epitaxial layer

Group III nitride semiconductor device and epitaxial substrate

Provided is a film deposition method capable of improving the crystal characteristic near an interface according to the lattice constant of a material that will constitute a thin film to be deposited. Specifically, a substrate is curved relative to the direction along one main surface on which the thin film is to be deposited, according to the lattice constant the material that will constitute the thin film to be deposited and the lattice constant of a material constituting the one main surface. The thin film is deposited on the one main surface of the substrate with the substrate curved.

Film deposition method

Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor () is provided with a supporting substrate () composed of gallium nitride, a buffer layer () composed of a first gallium nitride semiconductor, a channel layer () composed of a second gallium nitride semiconductor, a semiconductor layer () composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode (), a source electrode () and a drain electrode () for the transistor (). The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration Nof the first gallium nitride semiconductor is 4&#xd7;10cmor more. The carbon concentration Nof the second gallium nitride semiconductor is less than 4&#xd7;10cm.

High electron mobility transistor, field-effect transistor, and epitaxial substrate

Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be provided on a gallium nitride substrate of n type. A gallium nitride epitaxial film () is provided on a gallium nitride substrate (). A layer region () is provided in the gallium nitride substrate () and the gallium nitride epitaxial film (). An interface between the gallium nitride substrate () and the gallium nitride epitaxial film () is positioned in the layer region (). In the layer region (), a peak value of donor impurity along an axis from the gallium nitride substrate () to the gallium nitride epitaxial film () is 1&#xd7;10cmor more. The donor impurity is at least either silicon or germanium.

Vertical gallium nitride semiconductor device and epitaxial substrate

Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistoris provided with a supporting substratecomposed of gallium nitride, a buffer layercomposed of a first gallium nitride semiconductor, a channel layercomposed of a second gallium nitride semiconductor, a semiconductor layercomposed of a third gallium nitride semiconductor, and electrode structures (a gate electrode, a source electrodeand a drain electrode) for the transistor. The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration Nof the first gallium nitride semiconductor is 4&#xd7;10cmor more. The carbon concentration Nof the second gallium nitride semiconductor is less thancm.

Method of manufacturing group III Nitride Transistor

A semiconductor layer consisting of Ga.sub.1-x In.sub.x N.sub.y As.sub.1-y and/or GaN.sub.y As.sub.1-y and formed by incorporating nitrogen into a group III-V mixed crystal semiconductor is provided on a GaAs substrate. The hydrogen concentration in the semiconductor is kept at 5.times.10.sup.18 atoms/cm.sup.3 or below.

Growing community of inventors

Itami, Japan

Tatsuya Tanabe