Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Unicharm Corporation

Tatsuya Saeki

Satoru Tamada

Hiroaki Nakai

Jun Kudo

Akira Hosogane

Yasuhiro Kouro

Yoshitsugu Dohi

An apparatus for manufacturing an absorbent body for an absorbent article includes a conveying mechanism for conveying a continuous absorbent sheet, a slitting mechanism configured so that a plurality of slitting blades are pressed against the absorbent sheet conveyed by the conveying mechanism, the slitting blades extending in a predetermined direction, a cutting mechanism for cutting the absorbent sheet against which the slitting blades are pressed and forming the absorbent body, and a stretching mechanism arranged upstream of the cutting mechanism and for stretching, in a direction orthogonal to the predetermined direction, the absorbent sheet against which the slitting blades are pressed, and forming slits in the absorbent sheet.

Method of manufacturing absorbent article, manufacturing apparatus for absorbent body, and absorbent article manufactured thereby

The number of times of rewriting of memory cells is stored by number of rewrite (EW) times storage section. In data rewriting to memory cells, number of rewriting times data of a selected memory cell is transferred to and latched in a number of EW times sense latch section and transferred to a number of EW times counter. Controlling processor (CPU) sets a condition on a write pulse on the basis of a value obtained by updating a count value of the number of EW times counter and controls the operation of rewriting. In data rewriting, a count value after update of the number of EW times counter is transferred to the number of EW times sense latch section. The updated number of rewritings is transferred to a corresponding number of EW times storage section, in parallel to data rewriting to a memory cell.

Non-volatile semiconductor memory device

An internal voltage from an internal voltage generating circuit is transmitted to a pad in accordance with a control signal, and a buffer circuit coupled to the pad is set in an inactive state. The pad is connected to an external pin terminal via a bonding wire. Consequently, a semiconductor integrated circuit capable of monitoring and forcedly setting an internal voltage from an outside of the circuit device is realized with a minimum number of pin terminals without increasing the number of external pin terminals.

Semiconductor integrated circuit allowing internal voltage to be measured and controlled externally

There is provided a non-volatile semiconductor device having a memory cell in which a threshold value voltage changes in accordance with the application of the writing pulse having a predetermined width and voltage with respect to word lines and bit lines and data depending upon the threshold value voltage is written, wherein writing failure is generated in the first time data writing operation, and a writing condition is set for suppressing the writing condition is set which is capable of suppressing the writing failure rate than the case of the first time writing operation when the writing operation is re-executed.

Non-volatile semiconductor memory device capable of suppressing writing and erasure failure rate

The inventive flash memory comprises a memory cell array including nonvolatile memory cells and a control CPU controlling data writing, reading and erasing in the memory cell array and a multivalued flag part. The multivalued flag part stores a value indicating whether data written in any memory cell is binary data or multivalued data. The data can be read in a binary read sequence for the binary data or a multivalued read sequence for the multivalued data due to the value of the multivalued flag part.

Nonvolatile semiconductor memory device having structure storing multivalued data and data storage system comprising the nonvolatile semiconductor memory device

A power generating portion generates an erasing potential for an erasing operation with respect to information stored in a memory cell and variably generates a first potential applied to the selected memory cell and a second potential applied to the non-selected memory cell during a reading operation. A chip control portion selectively applies an erasing potential to every block to be erased. At the time, the chip control portion applies the first potential to any one of sectors in the block to be erased and also applies the second potential, which has been updated such that none of the memory cells belonging to the block to be erased is conductive, to the remaining sectors in the block to be erased for performing an erasing verify operation.

Growing community of inventors

Hyogo, Japan

Tatsuya Saeki