Semiconductor Energy Laboratory Co., Ltd.

Tatsuya Onuki

Shunpei Yamazaki

Kiyoshi Kato

Takanori Matsuzaki

Shuhei Nagatsuka

Takahiko Ishizu

Yuki Okamoto

Yuto Yakubo

Hajime Kimura

Tomoaki Atsumi

Hitoshi Kunitake

Wataru Uesugi

Munehiro Kozuma

Hiroki Inoue

Yutaka Shionoiri

Seiya Saito

Takayuki Ikeda

Daisuke Matsubayashi

Hidekazu Miyairi

Satoru Okamoto

Yoshinobu Asami

Minato Ito

Kei Takahashi

Hideki Uochi

Yuichi Sato

Tetsunori Maruyama

Shuhei Maeda

Naoaki Tsutsui

Kazuki Tsuda

Yuji Asano

Eri Sato

Hisao Ikeda

Hiromichi Godo

Susumu Kawashima

Hidetomo Kobayashi

Takeshi Aoki

Yutaka Okazaki

Katsuaki Tochibayashi

Masashi Oota

Kazuaki Ohshima

Tomokazu Yokoi

Satoru Ohshita

Toshiki Hamada

Yusuke Koumura

Shota Mizukami

The circuit layout generation system includes a memory portion, a limitation data arithmetic portion, and a layout data arithmetic portion. The memory portion is configured to store circuit connection data and first limitation data. The circuit connection data is data regarding connection of a transistor and a capacitor included in a pixel circuit. The first limitation data includes data that determines a wiring interval of the transistor and a wiring interval of the capacitor and data that determines placement coordinates of the transistor and the capacitor. The limitation data arithmetic portion is configured to generate second limitation data on the basis of the circuit connection data and the first limitation data and store the second limitation data in the memory portion. The second limitation data is data that determines the placement of the transistor and the capacitor designated by the placement coordinates so that the transistor and the capacitor are positioned close to each other. The layout data arithmetic portion is configured to generate layout data on the basis of the circuit connection data, the first limitation data, and the second limitation data.

Circuit layout generation system

A memory device with high storage capacity and low power consumption is provided. The memory device includes a first layer and a second layer including the first layer. The first layer includes a circuit, and the second layer includes a first memory cell. The circuit includes a bit line driver circuit and/or a word line driver circuit which transmits(s) a signal to the first memory cell. The first memory cell includes a first transistor, a second transistor, a conductor, and an MTJ element. The MTJ element includes a free layer. The free layer is electrically connected to the conductor. The first terminal of the first transistor is electrically connected to a first terminal of the second transistor through the conductor. The free layer is positioned above the conductor. The circuit includes a transistor containing silicon in a channel formation region, and each of the first transistor and the second transistor contains a metal oxide in a channel formation region.

Memory device and electronic device

A memory device occupying a small area is provided. In a memory cell including a reading transistor, a writing transistor, and a capacitor, the writing transistor is provided above the reading transistor. Alternatively, the reading transistor is provided above the writing transistor. An oxide semiconductor is used for a semiconductor layer where a channel of the writing transistor is formed. An oxide semiconductor is used for a semiconductor layer where a channel of the reading transistor is formed. Memory cells are arranged in a matrix.

Memory cell and memory device

An electronic device with a novel structure is provided. The electronic device includes a display apparatus, a gaze detection portion, and an arithmetic portion. The display apparatus includes a display portion divided into a plurality of sub-display portions and a functional circuit including a luminance conversion circuit. The gaze detection portion has a function of detecting the user's gaze. The arithmetic portion has a function of allocating the plurality of sub-display portions to a first section or a second section with the use of the detection result of the gaze detection portion. The functional circuit has a function of performing display on the sub-display portion included in the first section with a first driving frequency and performing display on the sub-display portion included in the second section with a second driving frequency lower than the first driving frequency. The luminance conversion circuit has a function of converting image data displayed on the second section to image data with reduced luminance to be displayed in the sub-display portion.

Electronic device

A semiconductor device with high reliability is provided. The semiconductor device includes a memory cell including a first ferroelectric capacitor and a reference memory cell including a second ferroelectric capacitor. In a first period, first binary data is written to the memory cell, and first reference binary data is written to the reference memory cell. In a second period, the first binary data is read from the memory cell, and the first reference binary data is read from the reference memory cell. In a third period, logic operation of the first binary data and the first reference binary data is performed. In a fourth period, second binary data is written to the memory cell, and second reference binary data is written to the reference memory cell. A value of the first binary data and a value of the second binary data are different from each other, and a value of the first reference binary data and a value of the second reference binary data are different from each other.

Driving method of semiconductor device

To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.

Semiconductor device

A semiconductor device having a novel structure is provided. The semiconductor device includes a first element layer including a first memory cell, a second element layer including a second memory cell, and a silicon substrate including a driver circuit. The first element layer is provided between the silicon substrate and the second element layer. The first memory cell includes a first transistor and a first capacitor. The second memory cell includes a second transistor and a second capacitor. One of a source and a drain of the first transistor and one of a source and a drain of the second transistor are each electrically connected to a wiring for electrical connection to the driver circuit. The wiring is in contact with a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor and is provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate.

Semiconductor device and electronic device having stacked element layers on driver-circuit substrate

A semiconductor device capable of measuring a minute current is provided. The semiconductor device includes an operational amplifier and a diode element. An inverting input terminal of the operational amplifier and an input terminal of the diode element are electrically connected to a first terminal to which current is input, and an output terminal of the operational amplifier and an output terminal of the diode element are electrically connected to a second terminal from which voltage is output. A diode-connected transistor that includes a metal oxide in a channel formation region is used as the diode element. Since the off-state current of the transistor is extremely low, a minute current can flow between the first terminal and the second terminal. Thus, when voltage is output from the second terminal, a minute current that flows through the first terminal can be estimated from the voltage.

Semiconductor device, semiconductor wafer, and electronic device

A high-resolution display device in which delay of input signals to pixels is reduced is provided. In the display device, a first layer, a second layer, and a third layer are formed in this order from the bottom. The first layer includes a driver circuit and a plurality of first wirings, the second layer includes a plurality of first contact portions, and the third layer includes a pixel array and a plurality of second wirings. The pixel array includes a plurality of pixel circuits. The plurality of second wirings are parallel to each other and extended in the column direction of the pixel array, and the plurality of pixel circuits are electrically connected to the plurality of second wirings. The driver circuit includes a plurality of output terminals positioned along a first direction. The plurality of first wirings are extended perpendicular to the first direction, and the plurality of output terminals are electrically connected to the plurality of first wirings. The plurality of first wirings are electrically connected to the plurality of second wirings through the plurality of first contact portions.

Display device and electronic device

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor. The transistor includes a first conductor, a first insulator over the first conductor, an oxide provided with a groove portion over the first insulator, a second conductor and a third conductor disposed in a region that does not overlap with the groove portion in the oxide, a second insulator disposed between the second conductor and the third conductor and in the groove portion in the oxide, and a fourth conductor over the second insulator. A bottom surface of the fourth conductor is lower than a bottom surface of the second conductor and a bottom surface of the third conductor. In a cross-sectional view of the transistor in the channel length direction, an end portion of a bottom surface of the groove portion has a curvature.

Semiconductor device having a groove portion in an oxide layer of a transistor channel

A semiconductor device having redundancy is provided. The semiconductor device includes a first driver circuit, a second driver circuit, a first selection circuit, a second selection circuit, and a switch circuit. An output terminal of the first driver circuit is electrically connected to an input terminal of the first selection circuit and a first terminal of the switch circuit, and an output terminal of the second driver circuit is electrically connected to an input terminal of the second selection circuit and a second terminal of the switch circuit.

Semiconductor device, display apparatus, and electronic device

A semiconductor device with a novel structure is provided. The semiconductor device includes a silicon substrate including a first circuit, a first element layer including a second circuit, and a second element layer including a third circuit. The first circuit includes a first transistor. The second circuit includes a second transistor. The third circuit includes a memory cell. The memory cell includes a third transistor and a capacitor. The first element layer and the second element layer constitute a stacked block stacked and provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate. A plurality of stacked blocks are stacked and provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. Each of the plurality of stacked blocks includes a first wiring provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. The plurality of stacked blocks are electrically connected to each other through the wiring.

A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. The first conductor is provided with a first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

Memory device

A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are provided to overlap with each other. Two bit lines included in the first bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. Two bit lines included in the second bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. In the first cell array, one of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair. In the second cell array, the other of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair.

Memory device including plurality of overlap memory cell arrays with folded bit-lines

A semiconductor device that can be miniaturized or highly integrated can be provided. The semiconductor device includes a first conductor positioned over a substrate; an oxide positioned in contact with atop surface of the first conductor; a second conductor, a third conductor, and a fourth conductor positioned over the oxide; a first insulator in which a first opening and a second opening are formed, the first insulator being positioned over the second conductor to the fourth conductor; a second insulator positioned in the first opening; a fifth conductor positioned over the second insulator; a third insulator positioned in the second opening; and a sixth conductor positioned over the third insulator. The third conductor is positioned to overlap with the first conductor. The first opening is formed to overlap with a region between the second conductor and the third conductor. The second opening is formed to overlap with a region between the third conductor and the fourth conductor.

Semiconductor device and method of manufacturing semiconductor device

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Kanagawa, Japan

Tatsuya Onuki