Fujitsu Corporation

Tatsuya Oku

Masato Hashizume

Yoshinori Nakamura

Kenji Fukunaga

Akihiro Yasuo

Satoshi Fukui

Hiroshi Nishida

Jinichi Yoshizawa

Takeshi Sasaki

Eiji Maeda

Hiroaki Mori

Nobuo Iguchi

Yasuo Takami

Tsuguo Okada

Miki Hagino

Yuuki Tsuji

Akira Yamamori

Masao Maeda

Yoshinori Okuda

A communication apparatus having a clock interface unit supplying a clock signal for synchronization, includes a clock extracting section for extracting a clock component from a receive signal, a decoding section for generating a decoded signal by decoding in a predetermined encoding form the clock component extracted by the clock extracting section, a frame converting section for creating a receive frame by converting the decoded signal to a frame in a predetermined frame form, a determining section for determining whether the predetermined encoding form and the predetermined frame form are right or not on a basis of the receive frame, a setting section for performing setting regarding the clock signal on a basis of the encoding form and frame form determined to be right by the determining section, and a clock signal output section for outputting the clock signal generated on a basis of the setting by the setting section.

Communication apparatus having clock interface

A disclosed network device includes a plurality of interface cards that receive clock signals and clock signal quality information from other devices via communication lines, respectively being predetermined communication line types corresponding to the plurality of interface cards, a controller that acquires the clock signal quality information and determines one of the clock signals having a highest quality based on this, and a clock processor that generates a synchronization clock signal used for network synchronization the clock processor, based on the determined one of the clock signals, whereby the clock processor includes a frequency measuring instrument that measures a frequency component of the one of the clock signals, and determines the communication line type corresponding to one of the interface cards, and a clock controller that provides a coefficient to a digital filter based on the determined communication line type.

Network device

In multi-connections, a message writing apparatus is provided. This message writing apparatus () comprises a path recognizing section (), a received message assembling section (), a receive control section (), an arbitrating section () and an external memory control section (). When a received ATM cell is written/readout in/from a receiving buffer, it is written/read out in a memory area corresponding to each path, which enables the processing of AAL5 messages from a plurality of paths and improves the transfer processing capability, thereby leading to realizing a shortening of the data transfer time.

Message writing apparatus, message writing method, message readout apparatus, message readout method, memory address control circuit for writing of variable-length message and memory address control circuit for readout of variable-length message

Printed circuit boardstoare connected in a star-like configuration with a single packet processing IC, connected to a CPU, at its center, each printed circuit board being connected to the packet processing IC by a high-speed supervisory control linehaving a sufficient transmission capacity to transfer therethrough transparent information and alarm transfer information as well as information from the central processing unit in packet form, and the transparent information and the alarm transfer information are communicated between the printed circuit boards via the high-speed supervisory control line and via the packet processing IC, with provisions made for the packet processing IC to detect a destination from the packet information received from the originating printed circuit board and to transmit the packet information to the terminating printed circuit board. Further, provisions are made to transmit packetized cells to the terminating printed circuit board in accordance with time priority, thereby achieving a transmission line terminating apparatus with a reduced number of wiring lines.

Transmission line terminating apparatus that performs packet processing

An interface apparatus for SDH/SONET interconnection includes a transmission interface section provided at a position where an apparatus of the SDH system and an apparatus of the SONET system face each other and adapted to transmit a signal toward an apparatus of a different system. The interface apparatus for SDH/SONET interconnection further includes a mode setting unit for setting a mode suitable for an apparatus of a counterpart system, a frame synchronization information inserting unit provided in the transmission interface section and adapted to insert frame synchronization information corresponding to the mode set by the mode setting unit, and an overhead information inserting unit provided in the transmission interface section and adapted to insert overhead information corresponding to the mode set by the mode setting unit. This structure makes is possible to easily interconnect apparatuses of different systems (apparatuses of the SDH system and the SONET system) so as to operate them.

Interface apparatus for SDH/SONET interconnection

Growing community of inventors

Kawasaki, Japan

Tatsuya Oku