Fujitsu Corporation

Tatsuya Ohori

Toshihide Kikkawa

Yoshihiro Arimoto

Isamu Hanyu

Fumitoshi Sugimoto

Hitoshi Tanaka

Ken-ichi Yanai

Hirosato Ochimizu

Tamotsu Wada

Nobuaki Tomesakai

Tatsuya Kakehi

Kazushige Shiina

Kohji Ohgata

Kanae Fukuzawa

Hiromi Ito

Tetsurou Hori

A method of fabricating a liquid crystal display device includes the step of removing a porous anodic oxide film selectively with respect to a barrier-type anodic oxide film covering a gate electrode pattern of a thin-film transistor, wherein the step of removing the porous anodic oxide film is conducted after the step of disconnecting a bridging conductor pattern used for supplying electric current at the time of anodic oxidation process of the gate electrode.

Fabrication process of a liquid crystal display device with improved

An electronic circuit having: a substrate with an upper surface; a lower level wiring made of conductive material and disposed on the substrate; an insulating cover film covering the surface of the lower level wiring; an interlayer insulating film formed on the substrate, covering the insulating cover film; an opening formed through the interlayer insulating film and the insulating cover film at an interlayer contact region extending from an area corresponding to the inside region, as viewed in the in-plane layout of the substrate, of the lower level wiring to an area corresponding to the outside region of the lower level wiring; and a higher level wiring disposed on a partial region of the interlayer insulating film and in the interlayer contact region, the higher level wiring being electrically connected to the lower level wiring in the interlayer contact region. The connection reliability between a lower level wiring layer and a higher level wiring layer in the connection region can be improved while maintaining the insulation reliability therebetween in the insulation region.

Electronic circuit device with multi-layer wiring

A compound semiconductor device constructed on a heteroepitaxial substrate includes a silicon substrate, a first compound semiconductor layer of a first compound semiconductor material provided on the silicon substrate as a buffer layer, a second compound semiconductor layer of a second compound semiconductor material having a lattice constant larger than that of the first compound semiconductor layer, and an active device provided on the second compound semiconductor layer, wherein the second compound semiconductor layer has a thickness exceeding a critical thickness above which dislocations develop due to the misfit in the lattice constant between the first and second compound semiconductor layers.

Compound semiconductor device constructed on a heteroepitaxial substrate

A semiconductor device includes a buffer layer of AlGaAs that contains oxygen with a concentration level in the approximate range of 8.times.10.sup.17 cm.sup.-3 to 6.times.10.sup.19 cm.sup.-3, and carbon with a concentration level in the approximate range of 2.times.10.sup.16 cm.sup.-3 to 2.times.10.sup.17 cm.sup.-3. A lattice constant of the AlGaAs buffer layer is larger than a lattice constant of the GaAs substrate so a lattice misfit of the AlGaAs layer with respect to the GaAs substrate is equal to or varies by no more than 2.times.10.sup.5 from a corresponding lattice misfit between an undoped AlGaAs crystal with respect to the GaAs substrate. Oxygen atoms occupy an interstitial site, creating a deep impurity level that suppresses side gate effect.

Semiconductor device having improved electronic isolation

An apparatus for growing a material at high temperature and employing a reaction gas. A reaction vessel is formed of a metal sidewall having outer and inner surfaces, the inner surface surrounding and defining a reaction chamber within the reaction vessel and which is generally vertically oriented. A cooling system maintains the metal sidewall of the reaction vessel at a temperature at which the metal does not produce contamination within the reaction chamber as a result of the high temperature operation, the reactant gases introduced into the reaction chamber or the product gases resultant from the reaction. A support mechanism includes a generally vertically oriented rod member which supports a susceptor, adapted to hold a wafer on which the material is to be grown, within the bottom part of the reaction chamber and, further, seals the reaction chamber. A sleeve is disposed closely adjacent to but spaced from the inner surface of the generally cylindrical metal sidewall portion and is of a material which remains stable at the high temperature of the reaction required for growing the material.

Deposition apparatus for growing a material with reduced hazard

E and D mode HEMTs are integrated in a laminated layer of pairs of GaAs/AlGaAs layers formed on the same GaAs-on-Si substrate. The gate electrodes of E and D mode HEMTs are formed on different GaAs layers. The GaAs layer on Si contains crystal defects. It is hypothesized that the defects extend upward in the laminated layer of pairs of GaAs/AlGaAs layers formed on the GaAs layer with such crystal defects. Etch pits are generated as the AlGaAs layer is etched by ammonium etchant. Generation of etch pits can be suppressed by etching the whole part of the exposed AlGaAs layer and exposing the GaAs layer under the gate electrode.

Compound semiconductor device on silicon substrate and method of

A method for growing an epitaxial layer of a group III-V compound semiconductor material that contains oxygen comprises the steps of supplying molecules of an organic compound that contains a group V element and oxygen in the molecule, and decomposing the molecules of the organic compound to release the group V element and oxygen.

Semiconductor device having an isolation region enriched in oxygen

A silicon-on-insulator (SOI) structure having a single crystal layer of a group III-V compound semiconductor material contacting a single crystal substrate of sapphire such that a principal surface of the single crystal layer establishes an intimate contact with a corresponding principal surface of the single crystal substrate and the single crystal layer, and the single crystal substrate are bonded with each other while elevating a temperature.

Composite semiconductor substrate having a single crystal substrate and

Semiconductor device having an isolation region enriched in oxygen and a

A Josephson logic circuit includes a Josephson element inserted between an input terminal and a reference electric potential such as ground, a resistor inserted between the input terminal and an input of the next stage of the Josephson circuit, and a current source which supplies an offset current to the Josephson element. By adjusting the offset current, the Josephson logic circuit can be operated as an AND circuit, an OR circuit, or a majority logic circuit having a high input sensitivity.

Josephson logic circuit

A method for fabricating an SOI structure which includes the steps of contacting a single crystal layer of a group III-V compound semiconductor material to a single crystal substrate of sapphire such that a principal surface of said single crystal layer establishes an intimate contact with a corresponding principal surface of said single crystal substrate and bonding the single crystal layer and the single crystal substrate with each other while elevating a temperature.

Composite semiconductor substrate and a fabrication process thereof

A first monocrystalline group III-V compound semiconductor layer is formed on an Si substrate. The surface of the first monocrystalline group III-V compound semiconductor layer is polished. A second monocrystalline group III-V compound semiconductor layer is grown on the polished surface by a metal organic chemical vapor deposition, by using as a group III source material at least partially a source material of group III atoms bonded to ethyl radical at the initial stage of growth, and thereafter by using as the group III source material a source material of group III atoms bonded to methyl radical. A grown layer with a flat surface can be obtained. The surface flatness can be improved further by adding In as a group III element.

Method of growing compound semiconductor

A heterojunction semiconductor device comprises a semi-insulating substrate, a channel layer comprising first and second sub-layers provided on the substrate for sustaining a two-dimensional carrier gas therein, a carrier supplying layer of a doped semiconductor material provided on the channel layer, a source electrode a drain electrode and a gate electrode provided on the carrier supplying layer. The first and second sub-layers have respective first and second saturation drift velocities of carriers such that the first saturation drift velocity is substantially larger than said second saturation drift velocity.

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Kawasaki, Japan

Tatsuya Ohori