Panasonic Corporation

Tatsuya Naruse

Atsushi Yamamoto

Tooru Matsui

Masanori Hirofuji

Hiroaki Segawa

Yoshifumi Kumashiro

An electrode pad is provided above a circuit block of a semiconductor integrated circuit device. A junction point A and a junction point B are provided on connection lines connecting electrode pads to an internal circuit and an electrostatic discharge (ESD) protection circuit. The junction point A and the junction point B are positioned at locations closer to the ESD protection circuit than to the electrode pads.

Semiconductor integrated circuit device

A semiconductor integrated circuit according to the present invention includes an I/O cell, a first PAD connected to the I/O cell, first and second PADs, a package wire which is connected to the first PAD and allows connection between the first PAD and an outside of the semiconductor integrated circuit, and a second package wire which is connected to the second PAD and allows connection between the second PAD and an outside of the semiconductor integrated circuit. A connection point between the first PAD and the fist package wire is located in an area where the I/O cell is placed. A connection point between the second PAD and the second package wire is located outside an area where the I/O cell is placed.

Semiconductor integrated circuit

The semiconductor integrated circuit of the present invention comprises: a standard cell group including a power supply wiring group or a ground wiring group, which is arranged at an interval based upon a design rule; a connection wiring that is provided in a same layer as the standard cell group for connecting between the power supply wirings or between the ground wirings; a strap wiring that crosses with the connection wiring three-dimensionally; and a connector body for interlayer-connecting the connection wiring and the strap wiring. The connector body has a shape different from that of the power supply wiring or the ground wiring.

Growing community of inventors

Osaka, Japan

Tatsuya Naruse