Fujitsu Corporation

Tatsuya Nagasawa

Hideyuki Iino

Seiji Suetake

Koichi Hatta

Koichi Kuroiwa

Takayoshi Taniai

Hiroyuki Fujiyama

Shinichi Utsunomiya

Noriko Kadomaru

Kenji Shirasawa

Makoto Miyagawa

An arithmetic operation unit for operating according to pipeline control and an instruction decoder for controlling the arithmetic operation unit by decoding an instruction, including a state retaining unit for retaining a state of the operation of the arithmetic operation unit, wherein the instruction decoder controls the execution of the arithmetic operation unit according to the information stored by the state retaining unit. A state is set when the decoder issues a signal for starting the arithmetic operation unit and the state is cleared when the decoder issues a signal for stopping the operation of the arithmetic operation unit. The arithmetic operation unit further comprises a unit for obtaining a maximum and a minimum value with a simple construction. A multiplier of the arithmetic operation unit comprises a unit for performing an addition of an exponential part of a multiplier and that of a multiplicand with a simple construction. The arithmetic operation unit further comprises a data packing and unpacking unit for packing and unpacking vector data. The data processing device is divided into several units and scan paths are divided into several paths corresponding to respective units.

Pipelined data processing device having improved hardware control over

A processor comprises a command storage unit for storing a plurality of commands and data received from outside the processor, a command interpreter for interpreting commands and data stored in the command storage unit, an address designator for designating a particular execution address of the storage unit according to a command interpreted by the command interpreter or to an operation start command, and an update selector for selecting whether or not to update the value of an execution address designated by the address designator according to a command interpreted by the command interpreter.

Coprocessor for performing an arithmetic operation by automatically

A slave processor for executing for example a vector operation is connected to a master processor. A vector length for a vector operation set to the slave processor can be changed without intervention of the master processor. When the master processor activates the slave processor, the slave processor outputs a busy signal immediately (at most one cycle later). The master processor reads the value of a busy register representing a busy/ready status of the slave processor in a slave access cycle at highest speed (in two cycles at most). Regardless of whether the master processor and the slave processor was designed as series products or general purpose products, they can be effectively connected.

Data processing apparatus for executing a vector operation under control

A semiconductor integrated circuit device includes a memory storing a microprogram used for controlling a desired function, a generator for generating an internal microprogram activating signal. A switching part selects either one of an external microprogram activating signal generated by an external device and the internal microprogram activating signal generated by the generator based on a first signal supplied from outside of the semiconductor integrated circuit device, thereby outputting a selected microprogram activating signal. A microaddress generator generates a microaddress of the microprogram stored in the memory. The microaddress generator is activated by the selected microprogram activating signal.

Semiconductor integrated circuit device which controls the activation of

Growing community of inventors

Kawasaki, Japan

Tatsuya Nagasawa