Elpida Memory, Inc.

Nec Corporation

Rambus Inc.

Ps4 Luxco S.a.r.l.

Longitude Semiconductor S.a.r.l.

Tatsuya Matano

Tadahiko Sugibayashi

Hiroshi Takada

Isao Naritake

Akiyoshi Seko

A charge pump circuit includes a first plurality of capacitors, and a first precharge circuit. The first plurality of capacitors are connected in parallel to each other. The first plurality of capacitors receive clock signals to perform sequentially pumping operations which generate a first higher voltage from a power voltage supplied. The first precharge circuit precharges a predetermined number of capacitors in the first plurality of capacitors at the power voltage. The predetermined number is greater than one.

Charge pump circuit

Disclosed herein is a device that includes: a data terminal; an output buffer coupled to the data terminal, the output buffer including a first output unit having a plurality of first output transistors of a first conductivity type and a second output unit having a plurality of second output transistors of a second conductivity type; and a calibration circuit including a first code generation unit that generates a first control code that controls an impedance of the first output unit by performing a first calibration operation based on an impedance of a first reference unit and a second code generation unit that generates a second control code that controls an impedance of the second output unit by performing a second calibration operation based on an impedance of a second reference unit. The calibration circuit performs the first and second calibration operations in parallel.

Semiconductor device having calibration circuit that adjusts impedance of output buffer

A semiconductor device includes first and second interconnects, a variable resistance element that may assume a first resistance value or a second resistance value in response to the current flowing therein, first and second transistors connected between the first and second interconnects in series with each other on both sides of the variable resistance element, and a power supply circuit unit that delivers the power supply to a control electrode of the first transistor. The power supply circuit unit supplies the power of a first power supply when the variable resistance element is to make transition to the first resistance value and the power supply circuit unit supplies the power of a second power supply when the variable resistance element is to make transition to the second resistance value, thereby allowing transitioning of the resistance values of the variable resistance element.

Semiconductor device

A device includes a first internal voltage generation circuit generating a first internal voltage in response to an external power supply voltage, a second internal voltage generation circuit generating a second internal voltage in response to the external power supply voltage, the second internal voltage being different in voltage level from the first internal voltage, and a preset signal generation circuit responding to a power-on of the external power supply voltage to the device and generating, independently of the first internal voltage, first and second preset signals that bring the first and the second internal voltage generation circuits into respective initial states, the preset signal generating circuit stopping generation of the first preset signal when the external power supply voltage reaches a first voltage level and stopping generation of the second preset signal when the external power supply voltage reaches a second voltage level different from the first voltage level.

Semiconductor apparatus

A semiconductor device includes: first transmission wirings each transmitting a small-amplitude signal between one of a plurality of first drivers and one of a plurality of receivers; a second transmission wiring transmitting a reference signal connected to each of the plurality of receivers; and a second driver outputting the reference signal with an impedance higher than an impedance with which each of the first drivers outputs the small-amplitude signal. The second transmission wiring is arranged between first and second power supply wirings corresponding to first and second potentials of the small-amplitude signal. The first and second potentials are supplied to each of the first drivers. The plurality of first transmission wirings are arranged close to each other, without being sandwiched between the first and second power supply wirings.

Semiconductor device and data processing system

A semiconductor device includes a first circuit block connected between first and second power lines, a logic circuit that receives an output signal of the first circuit block that is connected between the first power line and a fourth power line or a third power line and the second power line, and a second circuit block that receives an output signal of the logic circuit that is connected between the third and fourth power lines. In an active state, a first potential is supplied and in a standby state, a second potential lower than the first potential is supplied between the first and second power lines. In any of the active state and the standby state, the first potential is supplied between the third and fourth power lines. With this configuration, speeding-up of a critical path can be realized while maintaining a subthreshold current low.

Semiconductor device and data processing system including the same

A pair of power nodes of a logic circuit that needs to output a high level at the time of standby is connected to third and fifth dummy power lines and a pair of power nodes of a logic circuit that needs to output a low level at the time of standby are connected to second and sixth dummy power lines. Fourth, third, sixth, and fifth potentials of the second, third, fifth, and sixth dummy power lines satisfy fourth potential&#x3c;third potential&#x3c;first potential, and sixth potential&#x3e;fifth potential&#x3e;second potential. With this configuration, a leakage current flowing between a substrate and a gate of a transistor that becomes on at the time of standby, and a leakage current flowing between the substrate and a drain of a transistor that becomes off at the time of standby can be reduced.

A semiconductor apparatus includes a first internal voltage generator generating a first internal voltage in response to an external power supply voltage, a second internal voltage generator generating a second internal voltage in response to the external power supply voltage, the second internal voltage is larger in absolute value than the first internal voltage, and a preset signal generating circuit responding to a power-on of the external power supply voltage to the semiconductor apparatus and generating first and second preset signals which bring the first and second internal voltage generators into respective initial states, generation of the second preset signal is stopped after stopping generation of the first preset signal, in which the first internal voltage generator is released from its initial state in response to the stopping the generation of the first preset signal to be allowed to generate the first internal voltage, the second internal voltage generator is released from its initial state in response to the stopping the generation of the second preset signal to be allowed to generate the first internal voltage, and the second internal voltage is generated after generation of the first internal voltage.

A semiconductor device comprises an internal voltage generator circuit which includes a first transistor having a first and a second main electrode and a control electrode, a control circuit controlling a voltage between the second main electrode and the control electrode of the first transistor such that a voltage at the first main electrode of the first transistor remains at a predetermined voltage, and a second transistor having a first and a second main electrode and a control electrode. A voltage between the second main electrode and the control electrode of the first transistor is applied between the second main electrode and the control electrode of the second transistor.

Semiconductor device for supplying stable voltage to control electrode of transistor

In order to resolve a problem of the conventional technique in which there is a charge pump capacitance which is not used when a boosting method of the charge pump is changed, in a charge pump circuit unit, a connection switching terminal selects a power source voltage, a logically-inverting buffer gate and a capacitor to conduct an operation of boosting the power source voltage so as to be twice the power source voltage, and a connection switching terminal outputs the boosted voltage as a boost control voltage. In a charge pump circuit unit, a connection switching terminal selects the boost control voltage outputted from the charge pump circuit unit, and a logically-inverting buffer gate and a capacitor conduct an operation of boosting the inputted voltage so as to be 3&#xd7;VRD. An internal voltage is generated by outputting the boosted voltage to an internal power line via a NMOS transistor.

Boosting charge pump circuit

In a semiconductor apparatus, a power supply voltage generating circuit () and an internal circuit () using a power supply voltage generated by the power supply voltage generating circuit are supplied with different internal circuit preset signals (PRESETand PRESET) optimized for the power supply voltage generating circuit and the internal circuit, respectively.

In order to resolve a problem of the conventional technique in which there is a charge pump capacitance which is not used when a boosting method of the charge pump is changed, in a charge pump circuit unit, a connection switching terminal selects a power source voltage, a logically-inverting buffer gate and a capacitor to conduct an operation of boosting the power source voltage so as to be twice the power source voltage, and a connection switching terminal outputs the boosted voltage as a boost control voltage. In a charge pump circuit unit, a connection switching terminal selects the boost control voltage outputted from the charge pump circuit unit, and a logically-inverting buffer gate and a capacitor conduct an operation of boosting the inputted voltage so as to be 3&#xd7;VDD. An internal voltage is generated by outputting the boosted voltage to an internal power line via a NMOS transistor.

A semiconductor device includes an internal power supply line, a first power supply circuit, and second power supply circuits. The first power supply circuit includes an ordinary-voltage generation circuit supplying an ordinary voltage to the internal power supply line during an ordinary operation, and a test-voltage generation circuit supplying a test voltage to the internal power supply line during a test operation. Each of the second power supply circuits includes only an ordinary-voltage generation circuit. The number of ordinary-voltage generation circuits is thereby larger than the number of test-voltage generation circuits. Therefore, the ordinary voltage such as the precharge potential can be stably supplied to the internal power supply line while suppressing an increase in chip area.

Semiconductor device having a test-voltage generation circuit

A semiconductor memory device includes transistors that supply a higher write potential and a lower write potential to a sense amplifier, respectively, an overdrive transistor that supplies an overdrive potential to the sense amplifier, and a control circuit that changes a gate-source voltage of the overdrive transistor step by step. By raising a potential of one of paired bit lines to the overdrive potential not suddenly but step by step, an influence of a potential increase on the other bit line via a parasitic capacity is lessened and a malfunction caused by data inversion is prevented.

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Tokyo, Japan

Tatsuya Matano