Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Renesas Electronics Corporation

Matsushita Electric Industrial Co., Ltd.

Ryoden Semiconductor System Engineering Corporation

Tatsuya Kunikiyo

Katsumi Eikyu

Shigenobu Maeda

Masato Fujinaga

Kyoji Yamashita

Kenichiro Sonoda

Norihiko Kotani

Toshiaki Iwamatsu

Takashi Ipposhi

Yasuo Inoue

Takuji Matsumoto

Tetsuya Watanabe

Tadaharu Minato

Kazuyuki Sugahara

Kozo Katayama

Eiji Tsukuda

Hiroyuki Umimoto

Yosuke Takeuchi

Hidenori Sato

Yotaro Goto

Toshiki Kanamoto

Hisayuki Nishimura

Keiichi Itagaki

Mikio Ikeda

Junji Tateishi

Mutsumi Kobayashi

Katsuhiro Ohtani

Yoshinori Tanaka

Takeshi Hamamoto

Takeshi Okagaki

Kiyoshi Ishikawa

Fumitoshi Takahashi

Motoaki Tanizawa

Ken-ichiro Sonoda

In a solid state image sensor having two semiconductor substrates or more laminated longitudinally, electrical connection between the semiconductor substrates is made by a fine plug. An insulating film covering a first rear surface of a semiconductor substrate having a light receiving element, and an interlayer insulating film covering a second main surface of a semiconductor substrate mounting a semiconductor element are joined to each other. In its joint surface, a plug penetrating the insulating film and a lug embedded in a connection hole in an upper surface of the interlayer insulating film are joined, and the light receiving element and the semiconductor element are electrically connected through the plugs.

Solid state image sensor and manufacturing method thereof

A reduction is achieved in the power consumption of a solid-state imaging element including a photoelectric conversion element which converts incident light to charge and a transistor which converts the charge obtained in the photoelectric conversion element to voltage. A photodiode and a charge read transistor which are included in a pixel in the CMOS solid-state imaging element are provided in a semiconductor substrate, while an amplification transistor included in the foregoing pixel is provided in a semiconductor layer provided over the semiconductor substrate via a buried insulating layer. In the semiconductor substrate located in a buried insulating layer region, a p-type back-gate semiconductor region for controlling a threshold voltage of the amplification transistor is provided.

Semiconductor device

An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes an n-type semiconductor region formed in a p-type well, an n-type semiconductor region formed closer to a main surface of a semiconductor substrate than the n-type semiconductor region, and a p-type semiconductor region formed between the n-type semiconductor region and the n-type semiconductor region. A net impurity concentration in the n-type semiconductor region is lower than a net impurity concentration in the n-type semiconductor region. A net impurity concentration in the p-type semiconductor region is lower than a net impurity concentration in the p-type well.

Semiconductor device and manufacturing method thereof

Provided are a semiconductor device capable of detecting a light of each color with high accuracy without using a color filter, particularly enhancing detection accuracy of charges obtained by photoelectric conversion of a long-wavelength light, and manufacturing and control methods thereof. The semiconductor device has a p type semiconductor substrate, and first, second and third pixel regions. These regions each include a p type well region in the p type semiconductor substrate and an n type region configuring a pn junction therewith. The p type well region of the first pixel region is thinner, from the main surface to the lowermost portion, than that of the second and third pixel regions. On the side opposite to the main surface of the p type well region of the first and second pixel regions, a buried p type well region contiguous to the p type well region is further placed.

Semiconductor device, method of manufacturing same, and method of controlling semiconductor device

To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.

Manufacturing method of semiconductor device

A semiconductor device having a solid-state image sensor which can prevent inter-pixel crosstalk more reliably. The device includes: a semiconductor substrate having a main surface; a first conductivity type impurity layer located over the main surface of the substrate; a photoelectric transducer including a first conductivity type impurity region and a second conductivity type impurity region which are joined to each other over the first conductivity type impurity layer; and transistors which configure a unit pixel including the photoelectric transducer and are electrically coupled to the photoelectric transducer. At least part of the area around the photoelectric transducer in a plan view contains an air gap and also has an isolation insulating layer for electrically insulating the photoelectric transducer and a photoelectric transducer adjacent to it from each other. The isolation insulating layer abuts on the top surface of the first conductivity type impurity layer.

Semiconductor device with isolation insulating layer containing air gap

A CBCM circuit is capable of separately measuring each component of a measuring target capacitance. A node (N) is electrically connected to a terminal (P) between the drains of PMOS and NMOS transistors (MP, MN). As a target capacitance forming part, a coupling capacitance (C) is formed between the node (N) and a node (N). The node (N) is connected to a pad () through the terminal (P) and an NMOS transistor (MN), and a node (N) is connected to a terminal (P) between the drains of PMOS and NMOS transistors (MP, MN). A reference capacitance (C) is formed at the node (N) as a dummy capacitance. Currents (I, I) supplied from a power source to the nodes (N, N) are measured with current meters (), respectively and a current (I) induced from the node (N) and flowing to a ground level is measured with a current meter ().

Capacitance measurement circuit

PMISFETs and NMISFETs are placed in a capacitance measuring circuit. Each of interconnects is connected via the corresponding PMISFET through a charging voltage supply part to a power supply pad and via the corresponding NMISFET through a current sampling part to a current-monitoring pad. A current I can be measured by bringing a probe of an ammeter into contact with the current-monitoring pad.

An object is to reduce noise superimposed upon a signal carried on an interconnection or cross-talk. Dummy interconnections (and) are formed in the same layers respectively as interconnections (and) formed in a plurality of layers. The dummy interconnections (and) are connected through dummy plugs (and). At least the dummy interconnections (and) and the dummy plugs (and) are fixed at a ground potential.

A plurality of word lines (WL) are provided in parallel to one another and a plurality of bit lines (BL) are provided in parallel to one another, intersecting the word lines (WL) thereabove. MRAM cells (MC) are formed at intersections of the word lines and the bit lines therebetween. MRAM cells (MC) are provided so that an easy axis indicated by the arrow has an angle of 45 degrees with respect to the bit lines and the word lines. Thus, an MRAM capable of cutting the power consumption in writing is achieved and further an MRAM capable of reducing the time required for erasing and writing operations is achieved.

Magnetic memory device capable of passing bidirectional currents through the bit lines

There is provided a MRAM capable of reading at any timing information of memory cells at different addresses connected to the same bit line. Specifically, a memory cell of an address (AD) has MOS transistors (Q, Q) connected in series and a magnetic tunnel resistive element (MR), which are disposed between bit lines (BL, BL). The gate electrodes of the MOS transistors (Q, Q) are respectively connected to word lines (WL, WL). Memory lines (ML, ML) are connected in common to a reference voltage source (VR) via N-channel MOS transistors (Q, Q), and are respectively connected to current sources with a switch (S, S). The bit lines (BL, BL, BL, BL) are respectively connected to inputs of buffers with a switch (Bto B), and their outputs are supplied to the corresponding sense amplifier (SA).

Magnetic memory device

Growing community of inventors

Tokyo, Japan

Tatsuya Kunikiyo