Hitachi, Ltd.

Tatsuya Kawashimo

Hiroki Yamashita

Masayoshi Yagyu

Yoshio Miki

Fumio Yuuki

Hiroaki Fujii

Akihiro Takamura

Makoto Hanawa

A magnetic recording device capable of reducing the size of a writing circuit and the power consumption by readily adjusting the overshoot of the write current pulses is provided. Two or more transmission lines having different characteristic impedances are provided between an output driver having an impedance Zand a magnetic head, the transmission lines are formed so that the characteristic impedances Z, Z, and Z(n&#x2267;2) thereof on the output driver side are higher than those on the magnetic recording head side (Z&#x3e;Z&#x3e;Z), and the impedance Zof the output driver is equal to or higher than the characteristic impedance Zof the transmission line.

Magnetic recording device

This invention provides a signal transmission circuit, a signal output circuit, and a termination method of a signal transmission circuit capable of preventing the re-reflection of the signal at a transmitting node of a transmission path even when an impedance of a signal output circuit does not match a characteristic impedance of a transmission path. On a signal transmission circuit composed of a transmission path, a signal output circuit connected to a transmitting node of the transmission path, and a signal receiver circuit connected to a receiving node of the signal transmission path, in order to prevent the re-reflection of an output signal of a signal output unit at the transmitting node via the receiving node, a correction current generator unit is provided for outputting correction current with a predetermined current amount and at a predetermined timing set in a current amount/timing control section, to the transmitting node.

Signal transmission circuit, signal output circuit and termination method of signal transmission circuit

This invention provides a semiconductor device in which an ESD protection circuit and a termination circuit can be realized with a small die area. A PMOS transistor having an ESD protection function is placed between a signal node on a line from an signal terminal to an input buffer and a supply voltage node. Furthermore, a voltage generator circuit is placed to supply a reference voltage to the gate of the PMOS transistor. By the reference voltage controlled by the voltage generator circuit, a source drain resistance of the PMOS transistor is set. Thereby, the PMOS transistor can be made to function as a terminating resistor whose resistance can be set adaptively to a characteristic impedance of a transmission line, for example, connected to the signal terminal in addition to the ESD protection function.

Semiconductor device

A hierarchical server system efficiently balances the processing load thereon and for shortening the processing time therein is provided, such as a web server system. A system controller, a load balancing device, and a shared memory are provided in a multi-layer server system made of a plurality of servers. When processing implemented with a first layer server is temporarily stopped in order to acquire information needed for processing from a second layer server, process information needed to resume the processing is recorded in the shared memory. When the necessary information is sent back to the first layer server, the system controller inquires about work statuses of all first layer servers to select another first layer server to resume the processing based upon the inquiry results. The then selected first layer server then resumes the processing using the information that was sent back and the process information in the shared memory.

Hierarchical server system

The present invention provides a semiconductor integrated circuit capable of reducing a circuit area and a magnetic storage device using the same. The circuit in the present invention is provided with a single-stage output transistor for supplying write current to a magnetic head, a current source for outputting reference current of the write current, a diode-connected NMOS transistor for converting the current to gate voltage and having a certain device size ratio to the output transistor, a regulator circuit for transmitting gate voltage of the NMOS transistor and reducing output impedance, and a CMOS circuit for setting power supply voltage to an output of the regulator circuit and controlling the gate voltage of the output transistor. Then, this circuit is applied as a write circuit in a magnetic storage device.

Semiconductor integrated circuit and magnetic storage device using the same

A main logical unit and a standby logical unit are defined by a process controller in a shared main memory multiprocessor, and an information storage space accessible from both logical units is provided. The main logical unit stores address information onto that information storage space by indicating a memory area it controls as the main memory area. When failover or cloning becomes necessary, the standby logical unit searches the information on the applicable address. Then from the applicable information, it also searches information on the main memory area controlled by the main logical unit to establish in itself and forms a processing environment and state identical to the main logical unit such that the standby logical unit takes over all or a portion of the processing of the main logical unit. This enables the construction of a server system of high operability to overcome failures and poor response times by failover and cloning, etc.

Server system operation control method

Soft errors generated at an active time are reduced by adding a small-scale circuit to a high performance LSI, such as a processor without reducing the performance of the circuit. The processor has individual logic circuits each having a plurality of stages of logic gates for outputting true signals and complement signals for the individual logic gates. A latch circuit latches the true and complement signals of the logic circuits separately and a compare circuit detects for an error by comparing the true and complement output signals of the logic circuits to determine if they are at the same logical signal level or not, just upstream of the latch in which the individual true and complement output signals of the final logic circuit stages are individually latched. When the compare circuit detects an error because the true and complement output signals are at the same logical signal level, a recovery process is executed.

Growing community of inventors

Kokubunji, Japan

Tatsuya Kawashimo