Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Kioxia Corporation

Tatsuya Kato

Fumitaka Arai

Wataru Sakamoto

Yuta Watanabe

Katsuyuki Sekine

Satoshi Nagashima

Ryota Suzuki

Atsushi Murakoshi

Toshiyuki Iwamoto

Keisuke Kikutani

Fumie Kikushima

Mikiko Mori

Tatsuya Okamoto

Kohei Sakaike

Hiroshi Itokawa

Masato Endo

Yusuke Shimada

Takashi Kobayashi

Takayuki Ishikawa

Yasuhito Yoshimizu

Masaki Kondo

Makoto Fujiwara

Akio Kaneko

Masao Shingu

Masaaki Higuchi

Yoshiko Kato

Shinichi Sotome

Ken Komiya

Yefei Han

Katsumi Yamamoto

Koichi Sakata

Takashi Kurusu

Takeshi Murata

Muneyuki Tsuda

Tomofumi Inoue

Shunichi Takeuchi

A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.

Stacked-type semiconductor memory device

A semiconductor storage device includes: a first conductive layer extending in a first direction; a second conductive layer that is disposed apart from the first conductive layer in a second direction intersecting the first direction, and extends in the first direction; a plurality of semiconductor layers provided between the first conductive layer and the second conductive layer and arranged in the first direction, each of which includes a first portion facing the first conductive layer, and a second portion facing the second conductive layer; a plurality of first memory cells provided between the first conductive layer and the semiconductor layers, respectively; and a plurality of second memory cells provided between the second conductive layer and the semiconductor layers, respectively. A gap is provided between the two semiconductor layers adjacent in the first direction.

Semiconductor storage device

A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.

Semiconductor memory device

A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, a second insulating film provided between the second electrode and the first insulating film and on two first-direction sides of the second electrode, a third insulating film provided between the second electrode and the semiconductor pillar, and a conductive film provided inside a region interposed between the first insulating film and the second insulating film.

Semiconductor memory device and method for manufacturing same

A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.

According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.

Stacked type semiconductor memory device and method for manufacturing the same

Stacked type semiconductor memory device

A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin sheet portion disposed on the first electrode side, and a thick sheet portion disposed on the semiconductor pillar side. A length in the first direction of the thick sheet portion is longer than a length in the first direction of the thin sheet portion.

A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.

A semiconductor memory device according to an embodiment, includes a pair of first electrodes, a semiconductor pillar, an inter-pillar insulating member, a first insulating film, a second electrode, and a second insulating film. The pair of first electrodes are separated from each other, and extend in a first direction. The semiconductor pillar and the inter-pillar insulating member are arranged alternately along the first direction between the pair of first electrodes. The semiconductor pillar and the inter-pillar insulating member extend in a second direction crossing the first direction. The first insulating film is provided at a periphery of the semiconductor pillar. The second electrode is provided between the first insulating film and each electrode of the pair of first electrodes. The second electrode is not provided between the semiconductor pillar and the inter-pillar insulating member. The second insulating film is provided between the second electrode and the first electrode.

A semiconductor memory device of an embodiment includes a substrate, a first conductive layer provided above the substrate, the first conductive layer being spaced apart from the substrate in a first direction, and the first conductive layer being provided parallel to a substrate plane, a second conductive layer provided adjacent to the first conductive layer in a second direction intersecting the first direction, the second conductive layer being provided parallel to the substrate plane, a third conductive layer provided above the first conductive layer, the third conductive layer being spaced apart from the first conductive layer in the first direction, and the third conductive layer being provided parallel to the substrate plane, a fourth conductive layer provided above the second conductive layer, the fourth conductive layer being spaced apart from the second conductive layer in the first direction, and the fourth conductive layer being provided parallel to the substrate plane, a fifth conductive layer provided above the third conductive layer, the fifth conductive layer being spaced apart from the third conductive layer in the first direction, and the fifth conductive layer being provided parallel to the substrate plane, a sixth conductive layer provided above the fourth conductive layer, the sixth conductive layer being spaced apart from the fourth conductive layer in the first direction, and the sixth conductive layer being provided parallel to the substrate plane, an insulator provided between the first and second conductive layers, between the third and fourth conductive layers, and between the fifth and sixth conductive layers, a first signal line provided between the first, third, and fifth conductive layers and the insulator, the first signal line extending in the first direction, a second signal line provided between the second, fourth, and sixth conductive layers and the insulator, the second signal line extending in the first direction, a first memory cell provided between the first conductive layer and the first signal line, the first memory cell being configured to store first information, a second memory cell provided between the second conductive layer and the second signal line, the second memory cell being configured to store second information, a third memory cell provided between the third conductive layer and the first signal line, the third memory cell being configured to store third information, a fourth memory cell provided between the fourth conductive layer and the second signal line, the fourth memory cell being configured to store fourth information, a fifth memory cell provided between the fifth conductive layer and the first signal line, the fifth memory cell being configured to store fifth information, a sixth memory cell provided between the sixth conductive layer and the second signal line, the sixth memory cell being configured to store sixth information, and a control circuit configured to apply a second voltage to the third conductive layer, the control circuit being configured to apply a third voltage to the fifth conductive layer, the control circuit being configured to read data from the first memory cell, the second voltage being smaller than a first voltage, the first voltage being applied to the first conductive layer, and the third voltage being larger than the first voltage.

Semiconductor memory device and control method thereof

A semiconductor memory device includes a first NAND string and a second NAND string sharing a channel and being connected in parallel. When reading a value from a first memory cell transistor of the first NAND string, a first potential is applied to a gate of a second memory cell transistor of the first NAND string and a gate of at least one of fourth memory cell transistors opposing the second memory cell transistor, a second potential is applied to a gate of a third memory cell transistor of the second NAND string opposing the first memory cell transistor, and a gate potential of the first memory cell transistor is swept between the second potential and the first potential. The second potential is lower than the first potential.

Stacked type semiconductor memory device and method for reading the same

A semiconductor memory device includes a semiconductor member extending in a first direction, a first interconnect extending in a second direction crossing the first direction, and a first electrode disposed between the semiconductor member and the first interconnect. A curvature radius of a corner portion facing the semiconductor member in the first electrode is larger than a curvature radius of a corner portion facing the first interconnect in the first electrode.

Semiconductor memory device with floating gates having a curved lateral surface

In a semiconductor memory device, first insulating films are arranged along a first direction and a second direction and extend in a third direction. Interconnect is disposed between the first insulating films in the first direction and extends in the third direction. Electrodes are disposed between the first insulating films in the first direction on a second direction side of the interconnect, and is arranged along the third direction. Second insulating film is disposed between the interconnect and the electrodes. Semiconductor members are arranged along the third direction between the first insulating films in the second direction and extend in the first direction. The electrode is disposed between the interconnect and the semiconductor members. Third insulating film is disposed between the electrodes and the semiconductor member and is thicker than the second insulating film.

Growing community of inventors

Yokkaichi, Japan

Tatsuya Kato