Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Tatsuya Kanda

Hiroyoshi Tomita

Takahiko Sato

Toshiya Uchida

Tatsushi Otsuka

Ayako Sato

Shinnosuke Kamata

Hidenaga Takahashi

Tetsuo Miyamoto

Yoshinobu Yamamoto

Masanori Kurita

Satoru Shirakawa

Hiroyuki Kobayashi

Hitoshi Ikeda

Naoharu Shinozaki

Akihiro Funyu

Tomohiro Kawakubo

Syusaku Yamaguchi

Shinya Fujioka

Yasurou Matsuzaki

Yoshitaka Takahashi

Kotoku Sato

Toru Koga

Yoshiaki Okuyama

Jun Ohno

Hiroyuki Fujimoto

Takahiro Suzuki

Yukihiro Nomura

Masahiko Saitou

Osamu Hirooka

Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

Memory device, memory controller and memory system

An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

To perform mask control of data signals without increasing the number of external terminals even when the number of bits in a data mask signal is large, an address input circuit sequentially receives a first address signal, a second address signal, and a first data mask signal supplied to an address terminal in synchronization with transition edges of a clock signal. Namely, the first data mask signal is supplied to the address terminal at a different timing from timing at which the first and second address signals are received. The first address signal, second address signal, and first data mask signal are output, for example, from a controller accessing a semiconductor memory. A data input/output circuit inputs/outputs data via a data terminal and masks at least either of write data to memory cells and read data from the memory cells in accordance with logic of the first data mask signal.

Semiconductor memory and controller with time-shared mode for row address, column address and data mask signals inputted via address terminals

A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.

Semiconductor memory

A boost voltage generator generates a boost voltage as a high-level voltage of word lines. First word decoders output a low-level voltage or the high-level voltage according to a first address signal in an active period, and outputs the high-level voltage in a standby period. A switch circuit connects a high-level voltage line for supplying the high-level voltage to the first word decoders, with a boost voltage line in the active period, and connects the same with an internal voltage line in the standby period. The internal voltage line is supplied with a voltage lower than the boost voltage. Word drivers supply the boost voltage to the word lines when the gates of their transistors receive the low-level voltage from the first word decoders, and output the low-level voltage to the word lines when the gates thereof receive the high-level voltage from the first word decoders.

A semiconductor memory includes a refresh timer and an arbiter for determining the order of precedence between an access operation and a refresh operation, in order to automatically perform refresh operations inside the memory. A detecting circuit operates in a test mode and outputs a detection signal indicating that the refresh operation is yet to be performed, when a new internal refresh request occurs before the refresh operation is performed. For example, the detection signal is output when the interval of access requests is short and no refresh operation can be inserted between the access operations. That is, in the semiconductor memory in which refresh operations are performed automatically, it is possible to evaluate the minimum interval of supplying access requests. As a result, the evaluation time can be reduced with a reduction in the development period of the semiconductor memory.

Semiconductor memory having test function for refresh operation

The present invention is a self-test circuit (BIST) incorporated in the memory device, which is activated in response to a test activation signal from outside. When this self-test circuit is activated in response to a test activation signal (WBIZ) from outside, it generates a test operation command (WBI-CMD), generates a test address (WBI-ADD), and generates test data (WBI-DATA). Furthermore, after the self-test circuit writes the test data to a memory cell, it effects a comparison to establish whether or not the read data that is read from this memory cell is the same as the test data that was written thereto and stores information as to the result of this comparison. This comparison result information is then output to the outside.

Self-test circuit and memory device incorporating it

A semiconductor memory that can make the transition from a power-down state in a synchronous mode to an asynchronous mode without setting by a control register and that needs no extra circuits. A state selection section chooses, by selecting an existing internal signal the level of which changes in the power-down state or an existing internal signal the level of which does not change in the power-down state in accordance with a state selection signal inputted in advance and passing a signal selected to a synchronous/asynchronous mode setting section, whether the semiconductor memory should make the transition from the power-down state to a standby state in the synchronous mode or a standby state in the asynchronous mode. In accordance with the selection by the state selection section, the synchronous/asynchronous mode setting section generates a signal for causing the semiconductor memory to make the transition between the synchronous mode and the asynchronous mode.

Semiconductor memory capable of transitioning from a power-down state in a synchronous mode to a standby state in an asynchronous mode without setting by a control register

The present invention relates to a SDRAM and its control method which write or read data in synchronization with the external clock and its object is to provide a semiconductor memory device and its method which can be easily tested and evaluated by the conventional memory test equipment having a transfer type which transfers the data in synchronization with the rising and falling edges of the external clock. The semiconductor memory device has a write amplifier control section and I/O data buffer/register as a data transfer circuit corresponding to the data transfer type for the DDR type and SDR type. Also, a mode register is formed to be used as a switch signal to switch the data transfer circuit to either DDR type or SDR type.

Semiconductor memory device and method of controlling the same

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Kawasaki, Japan

Tatsuya Kanda