Panasonic Intellectual Property Management Co., Ltd.

Panasonic Corporation

Tatsuya Kabe

Hideyuki Arai

Mitsuyoshi Mori

Akito Inoue

Yusuke Sakata

Kentaro Nakanishi

Yuki Sugiura

Hisashi Aikawa

Masaki Tamaru

Takeshi Harada

Shinzo Koyama

Susumu Matsumoto

Hiroshi Koshida

Toru Hinomura

Naoki Torazawa

A substrate current suppression circuit includes: a fixed voltage line that supplies a fixed voltage to the collectors of the third and fourth transistors. The fixed voltage is a voltage higher than the base voltage of the third and fourth transistors when the first polarity is p type, and is a voltage lower than the base voltage when the first polarity is n type.

Substrate current suppression circuit, reference voltage generation circuit, and semiconductor device

A light detector is configured such that a light receiving portion having APDs and a peripheral portion are provided on a first principal surface of a p-type semiconductor substrate, and further includes a back electrode provided on a second principal surface of the semiconductor substrate and a p-type first separation portion provided between the light receiving portion and the peripheral portion. The APD has, on a first principal surface side, an n-type region and a p-epitaxial layer contacting the n-type region in a Z-direction. The peripheral portion has an n-type MISFET provided at a p-well and an n-well provided to surround entire side and bottom portions of the p-well.

Light detector

A light detector is configured such that a light receiving portion having APDs and a peripheral circuit portion are provided on a first principal surface of a p-type semiconductor substrate, and further includes a back electrode provided on a second principal surface of the semiconductor substrate and a p-type first separation portion provided between the light receiving portion and the peripheral circuit portion. The APD has, on a first principal surface side, an n-type region and a p-epitaxial layer contacting the n-type region in a Z-direction. The peripheral circuit portion has an n-type MISFET provided at a p-well and an n-well provided to surround side and bottom portions of the p-well.

A semiconductor devise includes a first substrate and a second substrate which are bonded each other. A first substrate includes an insulating first surface film as an uppermost layer, a first electrode and an insulating second surface film respectively formed inside a plurality of openings in the first surface film, and a first seal ring. A second substrate includes an insulating third surface film as an uppermost layer, and a second electrode, an insulating fourth surface film respectively formed inside a plurality of openings in the third surface film, and a second seal ring. The first electrode and the second electrode are directly bonded together. The first surface film and the third surface film are directly bonded together. The second surface film and the fourth surface film are directly bonded together. A seal ring formed of the first seal ring, the second surface film, the fourth surface film, and the second seal ring is continuous between the first substrate and the second substrate.

Semiconductor device and manufacturing method therefor

A semiconductor device includes: a first substrate including a first surface layer that includes first and second electrodes; a second substrate including a second surface layer that includes third and fourth electrodes, and directly bonded to the first substrate such that the second surface layer is in contact with the first surface layer; and a functional film provided between the second and fourth electrodes. The first and third electrodes are bonded together so as to be in contact with each other, and the second electrode, the functional film, and the fourth electrode constitute a passive element.

Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device includes: forming an interlayer insulating film on a substrate; forming a first hard mask formation film on the interlayer insulating film; altering the first hard mask formation film; after the altering of the first hard mask formation film, transferring an interconnect groove pattern to the altered first hard mask formation film to form a first hard mask made of the altered first hard mask formation film; and etching the interlayer insulating film using the first hard mask to form an interconnect groove in the interlayer insulating film. The first hard mask formation film is made of a metal film or a metallic compound film.

Method for fabricating semiconductor device

An interlayer insulating film containing oxygen and carbon is formed on a semiconductor substrate. A groove is formed in the interlayer insulating film. An auxiliary film containing predetermined first and second metallic elements is formed on a bottom surface and a sidewall of the formed groove. Then, an interconnect body layer containing copper is formed to fill the groove. By performing a thermal treatment, a first barrier film containing a compound of the first metallic element and an oxygen element of the interlayer insulating film, and a second barrier film containing a compound of the second metallic element and carbon element of the interlayer insulating film are formed on the interlayer insulating film on the bottom surface and the sidewall of the groove.

Growing community of inventors

Toyama, Japan

Tatsuya Kabe