Sandisk Technologies Inc.

Hitachi Global Storage Technologies Netherlands B.v.

Hgst Netherlands, B.v.

Renesas Technology Corp.

Hitachi Global Storage Technologies Japan, Ltd.

Tatsuya Hinoue

Hiroyuki Suzuki

Masanori Tsutsumi

Tomoo Yamamoto

Seiji Shimabukuro

Hidekazu Kashiwase

Yusuke Mukae

Naoki Takeguchi

Yotsuo Yahisa

Tetsuya Kanbe

Toshinori Ono

Kengo Kajiwara

Michiaki Sano

Ramy Nashed Bassely Said

Shunsuke Takuma

Tomoyuki Obu

Ryousuke Itou

Yujin Terasawa

Tomohiro Uno

Raghuveer S Makala

Rahul Sharangpani

Fei Zhou

Adarsh Rajashekhar

Zhixin Cui

Shiro Kamohara

Hiroshi Inaba

Akihiro Tobioka

Genta Mizuno

Yuki Kasai

Fumitoshi Ito

Yuji Totoki

Hiroshi Kanai

Hiroshi Yakushiji

Johann Alsmeier

Yanli Zhang

Hiroshi Ikeda

Akio Nishida

Ichiro Tamai

Satoshi Shimizu

Hiroaki Nemoto

Fumitaka Amano

Koji Sakamoto

Naohiro Hosoda

Kota Funayama

Takaaki Iwai

Fumiko Akagi

Yusuke Yoshida

Shigehisa Inoue

Keisuke Izumi

Masanori Terahara

Ryo Nakamura

Junpei Kanazawa

Takashi Yamaha

Joe Inagaki

Yu Ueda

Li Li

Jo Sato

Kenzo Iizuka

Atsushi Shimoda

Masae Suzuki, Legal Representative

Jo Inagaki

Akira Morinaga

Shogo Tomita

Hiroyuko Suzuki

A metal interconnect assembly includes a first metal interconnect structure, and a second metal interconnect structure embedded in a second dielectric material layer and containing a metal line portion having a top surface located within a first horizontal plane and having a bottom surface located within a second horizontal plane, and further containing a metal via portion adjoined to a bottom of the metal line portion and contacting a top surface of the first metal interconnect structure. The second metal interconnect structure contains a metallic liner including a first metallic material that includes an entire volume of the metal via portion and an outer part of the metal line portion, and a metallic fill material portion contains a second metallic material that includes an inner part of the metal line portion, does not contact and is spaced from the second dielectric material layer by the metallic liner.

High aspect ratio via fill process employing selective metal deposition and structures formed by the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a set of dielectric-metal-oxide blocking dielectric portions located at levels of the electrically conductive layers, a memory material layer, and a vertical semiconductor channel. Each of the electrically conductive layers includes a tubular metal nitride portion and a metal fill material portion, each of the tubular metal nitride portions laterally surrounds and contacts a respective one of the dielectric-metal-oxide blocking dielectric portions, and each metal fill material portion either contacts respective overlying and underlying insulating layers of the insulating layers, or contacts respective upper and lower metal nitride liner portions which have a smaller thickness than the tubular metal nitride portions.

Three-dimensional memory device and method of making thereof using selective metal nitride deposition on dielectric metal oxide blocking dielectric

Systems and methods for non-destructive inspection of semiconductor devices, such as three-dimensional NAND memory device, using reflective X-ray microscope computed tomographic (CT) imaging. An X-ray microscope directs a focused beam of X-ray radiation at an oblique angle onto the surface of a semiconductor wafer such that the beam passes through device structures and at least a portion of the beam is reflected by a semiconductor substrate of the wafer and detected by an X-ray detector. The wafer may be rotated about a rotation axis to obtain X-ray images of a region-of-interest (ROI) at different projection angles. A processing unit uses detected X-ray image data obtained by the X-ray detector at the different projection angles to generate a CT reconstructed image of the ROI. The CT reconstructed image may enable inspection of internal structural features, including embedded defects, in the semiconductor device in a non-destructive manner.

Systems and methods for non-destructive inspection of semiconductor devices using reflective X-ray microscope tomographic imaging

A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.

Three dimensional memory device and method of making thereof by forming channel and memory film after word line replacement

At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.

Three-dimensional memory device with backside support pillar structures and methods of forming the same

A conductive hard mask layer can be patterned with peripheral discrete openings. An anisotropic etch process can be performed to form peripheral discrete via cavities, which are subsequently expanded to form a continuous moat trench. An edge seal structure can be formed in the continuous moat trench. Alternatively, a conductive bridge structure may be formed prior to formation of a patterned conductive hard mask layer, and a moat trench can be formed around a periphery of the semiconductor die while the conductive bridge structure provides electrical connection between an inner portion and an outer portion of the conductive hard mask layer. The entire conductive hard mask layer can be electrically connected to a semiconductor substrate to reduce or prevent arcing during an anisotropic etch process that forms the peripheral discrete via cavities or the moat trench.

Semiconductor device having edge seal and method of making thereof without metal hard mask arcing

A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.

Three-dimensional memory device and method of making thereof using double pitch word line formation

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, a vertical stack of discrete silicon nitride memory elements located at levels of the electrically conductive layers, and a vertical stack of discrete silicon oxide blocking dielectric structures laterally surrounding the vertical stack of discrete silicon nitride memory elements. Each of the silicon oxide blocking dielectric structures includes a silicon oxynitride surface region, and an atomic concentration of nitrogen atoms within the silicon oxynitride surface region decreases with a lateral distance from an interface between the silicon oxynitride surface region and a respective one of the silicon nitride memory elements.

Three-dimensional memory device with discrete charge storage elements and methods for forming the same

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. The sacrificial material layers include a stack of word-line-level sacrificial material layers and at least one drain-select-level sacrificial material layer. Drain-select-level openings are formed through the at least one drain-select-level sacrificial material layer, which is replaced with at least one drain-select-level electrically conductive layer. Memory openings are formed by vertically extending the drain-select-level openings through the word-line-level sacrificial material layers. Memory opening fill structures are formed within the memory openings. The word-line-level sacrificial material layers are replaced with word-line-level electrically conductive layers.

Three-dimensional memory device with replacement select gate electrodes and methods of manufacturing the same

A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Memory openings, contact via cavities, or backside trenches may be used as access points for removing the sacrificial material layers.

A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory material layer. A vertical stack of insulating material portions can be provided at levels of the insulating layers to provide a laterally-undulating profile to the memory material layer. Alternatively, a combination of inner insulating spacers and outer insulating spacers can be employed to provide a laterally-undulating profile to the memory material layer.

Three-dimensional memory device including laterally-undulating memory material layers and methods for forming the same

Growing community of inventors

Yokkaichi, Japan

Tatsuya Hinoue