Sharp Kabushiki Kaisha Corporation

Tatsushi Yusuki

Kenichi Tanaka

Atsushi Miura

Katsuji Iguchi

Keizo Sakiyama

Shigeo Onishi

A semiconductor memory device which comprises unit memory cells each including two transistors each having a source/drain region and a gate electrode and one capacitor having a capacitor dielectric film, an upper electrode and a lower electrode, the gate electrode of each transistor being connected to a common word line, one source/drain region of each transistor being connected to a bit line and a reversed bit line respectively and the other source/drain region being connected to the upper electrode and the lower electrode respectively, and the bit line, the reversed bit line and the word line being disposed under the lower electrode of the capacitor.

Semiconductor memory device having two transistors and at least one

A semiconductor memory wherein a plurality of cells are arranged in a longitudinal direction of active regions, each cell having a node electrode and a contact hole for the node electrode, and a bit line contact region and the active region by half at the least on a semiconductor substrate having the active regions and word lines which are extended in a direction perpendicular to the longitudinal direction of the active regions, the bit line contact regions of adjacent bit lines are shifted by a quarter in the longitudinal direction between the adjacent cells in a direction in which the word lines are extended, and the projected shape of the node electrode is a polygon having more angles than a quadrangle which is substantially adapted as the node electrode and having at least one of interior angles set to be obtuse so that the projected area is substantially larger than that of the quadrangle.

Semiconductor memory with enhanced capacity

A semiconductor memory comprising a plurality of memory cells including transistors provided on a semiconductor substrate and capacitors having upper electrodes, insulating films and lower electrodes provided on the transistors, one terminal of the transistor of the memory cell being connected to the lower electrode of the capacitor, wherein the capacitors of the adjacent memory cells are opposed to each other, a part of the capacitors being superposed perpendicularly to the semiconductor substrate.

Growing community of inventors

Nara, Japan

Tatsushi Yusuki