Fujitsu Corporation

Tatsuru Matsuo

Takahisa Hiraide

Koji Maruhashi

Kenichiroh Narita

A learning method includes: acquiring input data and correct answer information, the input data including a set of multiple pieces of relationship data in which relationships between variables are recorded respectively; determining conversion rule corresponding to each of the multiple pieces of relationship data such that relationships before and after a conversion of a common variable commonly in the multiple pieces of relationship data are the same, when converting a variable value in each of the multiple pieces of relationship data into converted data rearranging the variable values in an order of input; converting each of the multiple pieces of relationship data into a multiple pieces of the converted data according to each corresponding conversion rule; and inputting a set of the multiple pieces of converted data to the neural network and causing the neural network to learn a learning model based on the correct answer information.

Computer-readable recording medium having stored therein learning program, learning method, and learning apparatus

A storage medium storing a program that causes a computer to execute a process, the process includes obtaining a plurality of test data used for analysis of a classifier; obtaining a plurality of approximation models approximated to the classifier, each of separation boundaries of the plurality of approximation models being approximated to a different part of a separation boundary of the classifier; specifying, for each of the approximation models, a test data having a highest similarity from among the test data; specifying, for each specified test data, an approximation model having a second highest similarity with the specified test data from among the approximation models; selecting, from among the approximation models, an exclusion target model whose error with the specified approximation model is the smallest for each specified test data; and outputting the plurality of approximation models from which the exclusion target model is excluded for each specified test data.

Storage medium, model output method, and model output device

A data transfer circuit has a first data transmission unit and two or more second shift registers. The first data transmission unit has a first shift register which has a plurality of first flip flop circuits which store data, shifts the data of the plurality of first flip flop circuits, and transmits data of two or more output terminals out of output terminals of the plurality of first flip flop circuits to the two or more second shift registers. The two or more second shift registers each shift data inputted from the two or more output terminals out of the output terminals of the plurality of first flip flop circuits.

Data transfer circuit

A data transfer circuit includes: a first power domain; a nonvolatile memory configured to store first data; a holding circuit; a readout circuit configured to read the first data from the nonvolatile memory and write the first data into the holding circuit at a time of chip reset; and a first controller configured to transfer the first data written into the holding circuit to the first power domain and make the holding circuit keep the first data at the time of chip reset, wherein the readout circuit, at a time of reset of the first power domain after the chip reset, does not read the first data from the nonvolatile memory, and the first controller transfers the first data held in the holding circuit to the first power domain.

Data transfer circuit and data transfer method

A clock signal is supplied to a first repair flag flip-flop, a second repair flag flip-flop, a first repair data flip-flop group, and a second repair data flip-flop group to serially transfer a second repair flag and a first repair flag stored in a non-volatile memory to the second repair flag flip-flop and the first repair flag flip-flop. Subsequently, repair data stored in the non-volatile memory is serially output to the first repair data flip-flop group, and repair data of the first repair data flip-flop group and the second repair data flip-flop group is serially transferred.

Memory device including redundant memory cell block

In a linear feedback shift register (LFSR), a four-bit shift register mainly using F/Fs is formed and an XOR circuit that feeds back an exclusive OR of a first bit and a last bit to the first bit is also provided, thereby outputting a test pattern having a maximum cycle of 15. A phase change circuit that can perform arbitrary phase change of a test pattern based on input of a control signal having a maximum clock number 4 and an average clock number log4 is also formed in the LFSR. As a result, a smaller clock count is required for the LFSR to output a test pattern that matches a test pattern automatically generated by an ATPG.

Pseudorandom number generator, semiconductor integrated circuit, pseudorandom number generator control apparatus, pseudorandom number generator control method, and computer product

A pattern correcting device corrects random test patterns generated by pseudo random number pattern generator (PRPG) into test patterns for a test to be input to shift registers. A pattern correcting device corrects the test patterns in unit of specified group, and individually releases correction of the test patterns when the correction in unit of the group is not appropriate. Furthermore, an unknown value mask device masks shift registers that output unknown values based on a control signal, and individually releases a mask of a shift register that outputs a fault value.

Semiconductor integrated circuit, test data generating device, LSI test device, and computer product

A semiconductor integrated circuit includes plural shift registers that receive plural test patterns randomly generated, respectively, a mask device that masks, among the shift registers, a target shift register specified by a mask pattern randomly generated. When a shift register other than the target shift register outputs an unknown value, the mask device masks the shift register according to a control signal. When the target shift register outputs a fault value, the mask device releases a mask of the target shift register according to a control signal.

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Kawasaki, Japan

Tatsuru Matsuo