Mitsubishi Electric Corporation

Tokyo Institute of Technology

Forschungsverbund Berlin E.v.

Createc Fischer & Co. Gmbh

Tatsuro Watahiki

Yohei Yuda

Akihiko Furukawa

Takuma Nanjo

Yuki Takiguchi

Satoshi Okuda

Hisashi Saito

Tetsuro Hayashida

Shinsuke Miyajima

Eiji Yagyu

Masahiro Yoshida

Tomohiro Tamaki

Hiroki Muraoka

Wolfgang Braun

Akifumi Imai

Kojiro Hara

Atsufumi Inoue

Marika Nakamura

Kengo Matsufuji

Shigeyoshi Usami

A first nitride semiconductor layer and a second nitride semiconductor layer are laminated in a first direction. The first and second nitride semiconductor layers form a heterojunction, and a two-dimensional carrier gas is induced in the first nitride semiconductor layer. A drain electrode is opposite to a source electrode via gate electrode in a third direction. The source electrode and the drain electrode conduct with the first nitride semiconductor layer. The first and second nitride semiconductor layers form a Schottky junction with the gate electrode. A first layer is located between the gate electrode and the drain electrode in the third direction and is in contact with the gate electrode, and is in contact with the second nitride semiconductor layer in a second direction. The first layer suppresses induction of the two-dimensional carrier gas in the first nitride semiconductor layer opposite to the first layer in the first direction.

Semiconductor device

The present invention relates to a heterojunction field effect transistor, and the heterojunction field effect transistor includes a barrier layer provided in an upper layer portion of a channel layer of a first nitride semiconductor, being formed of a second nitride semiconductor hetero-joined to the first nitride semiconductor, first and second impurity regions provided, being spaced each other with the barrier layer interposed therebetween, a source electrode and a drain electrode which are provided on the first and second impurity regions, respectively, an insulating film which is so provided as to come into contact with at least a region of the barrier layer excluding an edge portion thereof on the side of the source electrode, a gate insulating film which is in contact with the edge portion of the barrier layer and covers the insulating film, and a gate electrode which is so provided on the gate insulating film.

Semiconductor device and method of manufacturing the same

An object of the present invention is to suppress electrical contact between an outer peripheral portion of an intermediate electrode and a front surface electrode of a semiconductor chip without increasing the area of the semiconductor chip. A facing surface of the first intermediate electrode facing a first main electrode is smaller than a facing surface of the first main electrode facing the first intermediate electrode, and has an outer peripheral protective region and a connection region surrounded by the protective region. A pressure-contact semiconductor device includes a plurality of first conductor films partially formed in the connection region, and a first insulating film formed in regions in the connection region where no first conductor films are formed and in the protective region.

Pressure-contact semiconductor device

An object is to provide a technology that can enhance electrical characteristics of a semiconductor device. A semiconductor device is a semiconductor device provided with a semiconductor element. The semiconductor device includes: an n-type single-crystal gallium oxide layer including a first main surface; an electrode disposed on the first main surface of the n-type single-crystal gallium oxide layer or above the first main surface, the electrode being an electrode of the semiconductor element; a p-type oxide semiconductor layer disposed between the n-type single-crystal gallium oxide layer and the electrode; and an amorphous gallium oxide layer disposed between the n-type single-crystal gallium oxide layer and the p-type oxide semiconductor layer.

An object is to provide a semiconductor device that can prevent organic contamination of an electrode including a plurality of laminated metal layers. A semiconductor device includes: a semiconductor substrate; and an electrode including a plurality of layers laminated on a principal surface of the semiconductor substrate. The electrode includes: a first metal layer in contact with the principal surface of the semiconductor substrate, the first metal layer containing Al; an oxide layer formed on a surface of the first metal layer, the oxide layer containing a metal and oxygen; and a second metal layer formed on a surface of the oxide layer. Concentrations of the oxygen in the oxide layer are higher than or equal to 8.0&#xd7;10/cmand lower than or equal to 4.0&#xd7;10/cm.

Semiconductor device and method for manufacturing semiconductor device

Reliability of a gate resistor element during high-temperature operation is enhanced. A semiconductor device includes a drift layer, a base layer, an emitter layer, a gate insulation film, a gate electrode, a gate pad electrode, a first resistance layer, and a first nitride layer. A resistor of the first resistance layer has a negative temperature coefficient. The first resistance layer is made of hydrogen-doped amorphous silicon. The first nitride layer is made of a silicon nitride layer or an aluminum nitride layer.

Semiconductor device with differences in crystallinity between components

In order to provide a power semiconductor device reducing a leakage current due to a defect layer and having a small fluctuation in a threshold voltage, included are an n-type epitaxial film layer formed on a surface of the single crystal n-type semiconductor substrate and having a concave portion and a convex portion; an insulating film formed on a first region in a top portion of the convex portion; a p-type thin film layer formed on a surface of the insulating film and a surface of the n-type epitaxial film layer to form a pn junction between the p-type thin film layer and the n-type epitaxial film layer; and an anode electrode, at least part of which is formed on a surface of the p-type thin film layer and part of which passes through the p-type thin film layer and the insulating film.

Power semiconductor device

An object is to provide a technology for enabling prevention of deterioration of characteristics of an oxide semiconductor device. The oxide semiconductor device includes an n-type gallium oxide epitaxial layer, a p-type oxide semiconductor layer, and an oxide layer. The p-type oxide semiconductor layer is disposed above the n-type gallium oxide epitaxial layer, contains an element different from gallium as a main component, and has p-type conductivity. The oxide layer is disposed between the n-type gallium oxide epitaxial layer and the p-type oxide semiconductor layer, and is made of a material different from gallium oxide and different at least partly from a material of the p-type oxide semiconductor layer.

Oxide semiconductor device and method for manufacturing same

An n-type semiconductor layer has a single-crystal structure and is made of a wide-gap semiconducting material. A p-type semiconductor layer is provided on the n-type semiconductor layer and made of a material different from the aforementioned wide-gap semiconducting material, and has either a microcrystalline structure or an amorphous structure. An electrode is provided on at least one of the n-type semiconductor layer and the p-type semiconductor layer.

A semiconductor device includes a supporting substrate, a first GaN layer of a first conductivity type provided on the side of a first main surface of the supporting substrate, a second GaN layer of the first conductivity type provided on the first GaN layer, an AlxGa1&#x2212;xN layer provided on the second GaN layer, a third GaN layer of a second conductivity type provided on the AlxGa1&#x2212;xN layer, a fourth GaN layer of the first conductivity type provided on the third GaN layer, an insulating film covering a top of the fourth GaN layer, a trench gate reaching the inside of the second GaN layer, a gate electrode, a first main electrode connected to the third GaN layer, and a second main electrode, and the donor concentration of the third GaN layer is lower than that of the fourth GaN layer.

An oxide semiconductor device has an improved withstand voltage when an inverse voltage is applied, while suppressing diffusion of different types of materials to a Schottky interface. The oxide semiconductor device includes an n-type gallium oxide epitaxial layer, p-type oxide semiconductor layers of an oxide that is a different material from the material for the gallium oxide epitaxial layer, a dielectric layer formed to cover at least part of a side surface of the oxide semiconductor layer, an anode electrode, and a cathode electrode. Hetero pn junctions are formed between the lower surfaces of the oxide semiconductor layers and a gallium oxide substrate or between the lower surfaces of the oxide semiconductor layers and the gallium oxide epitaxial layer.

Oxide semiconductor device and method of manufacturing oxide semiconductor device

A substrate is made of gallium-nitride-based material. The n-type layer is disposed on a first surface of the substrate. A p-type layer is disposed on the n-type layer, and constitutes, along with the n-type layer, a semiconductor layer on the first surface of the substrate, the semiconductor layer being provided with a mesa shape having a bottom surface, a side surface, and a top surface. An anode electrode is disposed on the p-type layer. A cathode electrode is disposed on a second surface of the substrate. An insulating film continuously extends over the bottom surface and the top surface to cover the side surface. The top surface is provided with at least one trench. The at least one trench includes a trench filled with the insulating film.

A p-type oxide semiconductor is prevented from being oxidized by oxygen in an n-type oxide semiconductor even if the p-type oxide semiconductor is provided as a termination structure in the n-type oxide semiconductor. A semiconductor device includes an n-type gallium oxide substrate, an anode electrode joined to the n-type gallium oxide substrate, and a cathode electrode provided on the n-type gallium oxide substrate. Current flows between the anode electrode and the cathode electrode via the n-type gallium oxide substrate provided between the anode electrode and the cathode electrode. The semiconductor device further includes a p-type oxide semiconductor layer provided adjacent to a junction between the anode electrode and the n-type gallium oxide substrate, and a nitride layer provided between the p-type oxide semiconductor layer and the n-type gallium oxide substrate.

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Tokyo, Japan

Tatsuro Watahiki