Mitsubishi Denki Kabushiki Kaisha

Tatsuo Yamada

Masayuki Hata

Toyokatsu Nakajima

Hiromasa Nakagawa

Itsuko Ishida

A cache memory apparatus allocates memory regions on the basis of information attributes. The required memory region corresponding to the attribute is accessed before caching is implemented. This enables considerable reduction in apparatus that would otherwise be required to be duplicated among different chips corresponding to the number of information attributes. In a multiple data processing implementation, cache memory regions are allocated for each data processor. The required memory regions of the cache memory are accessed in accordance with information specifying the data processor before caching is carried out. To avoid data collision when the main memory data is substantially rewritten, and when data having the same address and different access types exist simultaneously, data representing the type of access is stored. In response to a change in access, all data signals stored in each ways is nullified so that a plurality of data stored in the memory regions is not simultaneously output.

Memory apparatus and method capable of setting attribute of information

A computer system is provided with a plurality of cache memories. Each cache memory stores data corresponding to part of main memory address space without overlapping with each other, thereby enabling capacity of the cache memory to be increased with ease. An address mask register is used to allocate the portion of main memory address space stored in each cache.

Computer system with cache memory having address mask register

A memory array and associated control circuitry in which the cells of the array can be accessed according to at least two addressing configurations. A multiple-bit bit address can be applied directly to an address decoder or, responsive to control signals, the bits of the address can be rearranged before being applied to the decoder. Additionally, the width of the accessed word can be increased by optionally ignoring some of the address bits but then increasing the number of bits accessed in parallel.

Alternatively addressed semiconductor memory array

A semiconductor IC device of an asynchronous bus type which is in a selected state when a chip select signal applied to it is at a 'H' level, comprises an external control signal line through which an external control signal is input, and a first and a second internal control signal lines for transfer of a first and a second control signals each of which is not activated when the other is activated. The first control signal is allocated to either the 'H' level or the 'L' level of the external control signal, and the second control signal is activated when the external control line is at the second level which is the inverse of the first level for the first control signal. An inhibit circuit is provided to prevent the second control signal from being erroneously activated while the first control signal is to be activated and when the first level of the external control signal begins after or terminates before the chip select signal.

Synchronous bus type semiconductor circuit wherein two control signals

A shift register which, including a plurality of cells each comprising a data latch section and a shift control section, operates without external clocks, wherein the shift control section includes a terminal for receiving a shift start control signal; a terminal for receiving a shift inhibition control signal; a shift allowance control circuit which receives signals indicating as to whether each of the particular cell and the cells adjacent thereto is in a shift operation and signals indicating as to whether each of the adjacent cells is in a state which allows the shift of the particular cell, and generates a shift allowance signal to be given to the particular cell and the adjacent cells on the basis of the states of these cells and the shift inhibition control signal; a shift control circuit which receives the shift start control signal, the output of the shift allowance control circuit, the state signals of the particular cell and the adjacent cell, and makes the data latch section to conduct a shift operation as well as outputs an in-shift-operation signal of the particular cell against the shift control circuit of the adjacent cell; and a shift conclusion control circuit which receives the shift inhibition control signal and the state signals of the particular cell and the adjacent cell, and outputs a signal for ordering to conclude the shift operation to the shift control circuit of the particular cell and a signal indicating the conclusion of shift operation to that of the adjacent cell.

Shift register

An input amplifier circuit, specifically, an input amplifier circuit for logic signals, in which noise signal components having a duration less than a predetermined duration are eliminated from the output signal of the amplifier. A delay circuit is added to the feedback loop of a Schmitt trigger amplifier circuit which has a delay time equal to the predetermined delay. The delay circuit effectively inhibits the output signal from changing state unless the input signal has a duration greater than the predetermined duration.

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Hyogo-ken, Japan

Tatsuo Yamada