Kabushiki Kaisha Toshiba

Sony Computer Entertainment Inc.

Tatsuo Teruyama

Itaru Yamazaki

Jin Satoh

Rakesh Agarwal

Kamran Malik

A drawing apparatus includes a reception unit, a first holding unit and a drawing processing unit. The reception unit receives graphic information. The first holding unit holds a plurality of first data which is a part of the graphic information received by the reception unit, in association with identification numbers assigned to the first data. The drawing processing unit draws a graphic on the basis of the first data held in the first holding unit. The drawing processing unit uses the plurality of the first data in a same task to draw the graphic. The reception unit records the identification numbers of the first data and a synchronization flag in order of reception. The synchronization flag is set for the first data received first among the plurality of first data processed by the same task in the drawing processing unit.

Drawing apparatus and method for processing plural pixels in parallel

A processing apparatus includes an execution stage which executes each of instruction streams, a first resource counter which counts the number of operating resources used when the execution stage executes a first one of the instruction streams, a second resource counter which holds data of the number of unused ones of the operating resources, and a control circuit which reads the count value of the first resource counter from a management table when a subsequent instruction stream is executed, to control a start of execution of the subsequent instruction stream in accordance with a subtraction result obtained by subtracting the count value from the data. The control circuit checks whether a number of operating resources required by the subsequent instruction stream is secured based on the subtraction result before the subsequent instruction stream starts to be executed.

Processing apparatus

An instruction rollback processor system according to the present invention is provided. The instruction rollback processor system includes: an instruction window buffer storing a plurality of instructions not yet executed and are arranged in a predetermined order; a multiplexer receiving an output of the instruction window buffer; and a rollback unit connected between the output side of the multiplexer and another input of the multiplexer.

Instruction rollback processor system, an instruction rollback method and an instruction rollback program

There is disclosed a bypass control method in which data can be set on a source register of an instruction to be executed on an instruction bus in a short time. A bypass control apparatus of the present invention includes a plurality of comparators for comparing the outputs of flip-flops for transferring a register number of a destination register on the instruction bus with each other. By utilizing a comparison result of a comparator for comparing the comparison results of these comparators with the register number of the source register on the instruction bus, a bypass path of data inputted to the source register of the instruction to be executed can be set in a short time. When a plurality of agreements are detected, the bypass path is set on the basis of the output of the flip-flop on a first stage side, so that it is possible to avoid a disadvantage inputting old data to the source register by mistake.

Bypass control circuit

A bypass logic circuit ( ) generates select signals (SelRs , SelRt , SelRs and SelRt ) by using prediction result flags (PrdNTkn A and PrdNTkn D) which are results of prediction about branch, instead of a branch condition not-taken signal (NTknA) actually output from a branch unit ( ). Bypass multiplexers ( ) select operands to be output to ALU ( ) or the branch unit ( ) on the basis of these select signals (SelRs , SelRt , SelRs and SelRt ). Therefore, ample time is given for generating these select signals (SelRs , SelRt , SelRs and SelRt ).

Processor which executes pipeline processing having a plurality of stages and which has an operand bypass predicting function

A processor includes n-bit (e.g., 128-bit) register circuitry for holding instruction operands. Instruction decode circuitry decodes processor instructions from an instruction stream. Arithmetic logic (AL) circuitry is operable to perform one of a single operation on at least one m-bit maximum (e.g., 64-bit) operand provided from the n-bit register circuitry, responsive to a first single processor instruction decoded by the instruction decode circuitry, wherein m<n. In addition, the AL circuitry is operable to perform multiple parallel operations on at least two portions of one n-bit operand provided from the n-bit register circuitry. The multiple parallel operations are performed responsive to a second single instruction decoded by the instruction decode circuitry.

Processor method and apparatus for performing single operand operation and multiple parallel operand operation

An instruction fetch unit,issues a normal ALU operating instruction or a wide ALU operating instruction using two operating units to a first pipeline,. The instruction fetch unit,also issues a normal ALU operating instruction to a second pipeline,. Occasionally, a wide ALU operating instruction using both a first integer unit,and a second integer unit,to the first pipeline,while a normal ALU operating instruction using the second integer unit,to the second pipeline,. In this case, if the normal ALU operating instruction is earlier, then the normal ALU operating instruction is executed preferentially. If the wide ALU operating instruction is earlier, then the wide ALU operating instruction is executed preferentially.

Processor having operating instruction which uses operation units in different pipelines simultaneously

A data transfer device for controlling data transfer among memories includes a first bus control section for transferring addresses to the first memory through a first address bus, and for controlling input and output of a group of first control signals required to access the first memory. Also included is a second bus control section for transferring addresses in the second memory through the second address bus, and for controlling input and output of a group of second control signals required to access the second memory. A control circuit is used for inputting addresses on the first bus, addresses on the second bus, the group of first control signals and the group of second control signals, and selecting one of them based on the control signals from the first bus control section to supply the first memory, and for executing data transfer in one cycle by executing simultaneous address specification to the first bus control section and the second bus control section.

Growing community of inventors

Kawasaki, Japan

Tatsuo Teruyama