Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Other

Symetrix Corporation

Kojundo Chemical Laboratory Co., Ltd.

Tatsuo Otsuki

Koji Arita

Shinichiro Hayashi

Yasuhiro Shimada

Carlos Alberto Paz De Araujo

Eiji Fujii

Yasuhiro Uemoto

Akihiro Matsuda

Toru Nasu

Atsuo Inoue

Yoshihisa Nagano

Taketoshi Matsuura

Larry D McMillan

Michael C Scott

Masamichi Azuma

Vikram Joshi

Yoshihisa Kato

Joseph D Cuchiaro

Narayan Solayappan

Hidekimi Kadokura

Kiyoshi Uchiyama

Myoungho Lim

Zheng Chen

Ikuko Aoki

Masamichi Matsumoto

Akio Shimano

Yoshihiro Shimada

Yukoh Hochido, Deceased

Hiromitsu Aoki

A ferroelectric memoryincludes a group of memory cells (), each cell having a ferroelectric memory element (etc.), a drive line (etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (etc.) between the memory cells and the bit line, a set switch (etc.) connected between the drive line and the memory cells, and a reset switch (etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.

Ferroelectric memory and method of operating same

A semiconductor memory device includes a field-effect transistor with a gate electrode that has been formed over a semiconductor substrate with a ferroelectric layer interposed between the electrode and the substrate. The device includes a first insulating layer, which is insulated against a leakage current more fully than the ferroelectric layer, between the ferroelectric layer and the gate electrode.

Semiconductor memory device

A ferroelectric thin film capacitor has smooth electrodes permitting comparatively stronger polarization, less fatigue, and less imprint, as the ferroelectric capacitor ages. The smooth electrode surfaces are produced by carefully controlled drying, soft baking, and annealing conditions.

Thin film ferroelectric capacitors having improved memory retention through the use of essentially smooth bottom electrode structures

A ferroelectric device includes a ferroelectric layer and an electrode. The ferroelectric material is made of a perovskite or a layered superlattice material. A superlattice generator metal oxide is deposited as a capping layer between said ferroelectric layer and said electrode to improve the residual polarization capacity of the ferroelectric layer.

Ferroelectric device with capping layer and method of making same

A ferroelectric FET having an interface insulator layer containing ZrO . The ferroelectric FET includes a gate oxide layer, the interface insulator layer is located on the gate oxide layer, and ferroelectric layered superlattice material is located on the interface insulator layer, The interface insulator layer has a thickness of from 15 to 25 nanometers.

Ferroelectric field effect transistor

A Ti/TiN adhesion/barrier layer is formed on a substrate and annealed. The anneal step is performed at a temperature within a good morphology range of 100&deg; C. above a base barrier anneal temperature that depends on the thickness of said barrier layer. The base barrier anneal temperature is about 700&deg; C. for a barrier thickness of about 1000 &angst; and about 800&deg; C. for a barrier thickness of about 3000 &angst;. The barrier layer is 800 &angst; thick or thicker. A first electrode is formed, followed by a BST dielectric layer and a second electrode. A bottom electrode structure in which a barrier layer of TiN is sandwiched between two layers of platinum is also disclosed. The process and structures also produce good results with other capacitor dielectrics, including ferroelectrics such as strontium bismuth tantalate.

Integrated circuit capacitors with barrier layer and process for making the same

A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm,or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10,atoms/cm,or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

Semiconductor device having a capacitor exhibiting improved moisture resistance

Semiconductor device having capacitor and manufacturing method thereof

A method for forming an interface insulator layer in a ferroelectric FET memory, in which a liquid precursor is applied to a semiconductor substrate. Preferably, the liquid precursor is an enhanced metalorganic decomposition (&ldquo;EMOD&rdquo;) precursor, applied using a liquid-source misted deposition technique. Preferably, the EMOD precursor solution applied to the substrate contains metal ethylhexanoates containing metal moieties in relative molar proportions for forming an interface insulator layer containing ZrO,, CeO,, Y,O,or (Ce,Zr,)O,, wherein,x&lE;

Method for fabricating ferroelectric field effect transistor having an interface insulator layer formed by a liquid precursor

Semiconductor device having a passivation layer which minimizes diffusion of hydrogen into a dielectric layer

A ferroelectric field effect transistor memory cell includes a thin film varistor located between the gate electrode and the ferroelectric layer. The varistor protects the ferroelectric layer from disturb voltage pulses arising from memory read, write and sense operations. A second electrode is located between the thin film varistor and the ferroelectric layer. The thin film ferroelectric is positioned over the channel of a transistor to operate as a ferroelectric gate. For voltages at which disturb voltages are likely to occur, the thin film varistor has a resistance obeying a formula R.sub.d &gt;10.times.1/(2.pi.fC.sub.F), where R.sub.d is resistivity of the thin film varistor, f is an operating frequency of said memory, and C.sub.F is the capacitance of the ferroelectric layer. For voltages at or near the read and write voltage of the memory, the thin film varistor has a resistance obeying a formula R.sub.d &lt;0.1.times.1/(2.pi.fC.sub.F).

Ferroelectric memory with disturb protection

A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

Growing community of inventors

Osaka, Japan

Tatsuo Otsuki