Nec Corporation

Kabushiki Kaisha Nihon Micronics

Sony Corporation

Guala Technology Co., Ltd.

Kabushiki Kaisha Toshiba

Other

Nippon Telegraph and Telephone Corporation

Fuji Electric Co., Ltd.

Molex Corporation

Toshiba Electronic Devices & Storage Corporation

Micronics Japan Co., Ltd.

Tatsuo Inoue

Osamu Arai

Hidehiro Kiyofuji

Akira Nakazawa

Kazuyuki Tsunokuni

Yoichi Toriumi

Kiyoyasu Hiwada

Takuo Kudoh

Toshiyuki Kudo

Katsushi Mikuni

Takashi Tonokawa

Mitsuru Nitta

Tomokazu Saitoh

Hideki Yoshida

Shinsuke Kunishi

Yuki Saito

Yoshiyuki Kunito

Tsutomu Niimura

Mitsuru Kimura

Akihisa Akahira

Yuji Miyagi

Kiyotoshi Miura

Moriyasu Banno

Kenji Sasaki

Yasuhiro Katayama

Michihiko Sakurai

Toshinori Omori

Shozo Izumo

Nobuaki Terakado

Tatsuo Satoh

Michitomo Yamaguchi

Takayasu Sugai

Kazunori Aoki

Tetsuro Yamashita

Nobuo Uda

Katsu Inaga

Daisuke Katori

Naoki Oshima

Shogo Masuda

Masaaki Tanabe

Yoichi Sakai

Takashi Hoshi

Takeshi Kamakura

Teruaki Iijima

Hiroshi Nishinaga

Juri Ogasawara

Chad R Seibel

Masatoshi Yokouchi

Issei Sakurada

Norihiro Imai

Kohji Tonokawa

A semiconductor device comprises a central processing device, a first logical circuit, and a serial memory interface circuit. The first logical circuit has a first scan chain in which a first scan pattern is set, is configured to suppress a leakage current when the first scan pattern for power saving is set in the first scan chain. The serial memory interface circuit is configured to acquire the first scan pattern for power saving from an external storage device. The leakage current of the first logical circuit is suppressed by transferring the first scan pattern for power saving acquired by the serial memory interface circuit to the first logical circuit and setting the first scan pattern for power saving in the first scan chain under control of the central processing device.

Semiconductor device and control method of semiconductor device

A method for manufacturing oxide semiconductor secondary cells concurrently and evenly on a plurality of chips. A method for manufacturing a chip on which an oxide semiconductor secondary cell is mounted, the oxide semiconductor secondary cell that is formed by layering a first electrode, a charging function layer, and a second electrode being layered on a circuit. The method includes a layering process to layer and form the oxide semiconductor secondary cells integrally at regions corresponding to a plurality of chips formed on a wafer without separately forming oxide semiconductor secondary cells at regions corresponding to the respective chips, and a separating process to perform separation into individual oxide semiconductor secondary cells corresponding to the respective chips by performing pattern etching on the integrally-formed oxide semiconductor secondary cells to eliminate regions not corresponding to the respective chips except for regions corresponding to the respective chips.

Secondary battery mounted chip manufacturing method

Provided is a secondary battery which is small in size and in which current capacity per unit volume can be increased. The present invention provides a secondary battery including two cell units each including a charging layer between a first electrode layer and a second electrode layer, the two cell units being parallel-connected by juxtaposing and connecting a first electrode layer of one cell unit and a first electrode layer of the other cell unit or a second electrode layer of the one cell unit and a second electrode layer of the other cell unit, and by wire-connecting the second electrode layer of the one cell unit and the second electrode layer of the other cell unit or the first electrode layer of the one cell unit and the first electrode layer of the other cell unit.

Secondary battery

A secondary battery-mounted circuit chip wherein secondary battery is directly fabricated on opposed surface of formed circuit into an integrated structure of the secondary battery and circuit, and a manufacturing method thereof. Secondary battery-mounted circuit chip is configured such that secondary battery is directly fabricated in region corresponding to circuit into integrated structure of secondary battery and circuit. The chip is secondary battery-mounted circuit chip wherein secondary battery is formed on surface opposing a circuit region fabricated on wafer. Secondary battery and circuit are formed into integrated structure by forming the uppermost part of circuit having multilayer wiring into secondary battery structure on upper part of circuit surface subjected to passivation, forming secondary battery directly stacked by making uppermost wiring layer of multilayer wiring part of circuit in a surface structure to be used in common, or forming secondary battery on rear surface of substrate having the circuit formed thereon.

Secondary battery-mounted circuit chip and manufacturing method thereof

A structure with suppressed thickness and high-density when battery cells of a thin-film-solid secondary battery are stacked. Adjacent battery cells are stacked such that negative electrodes are in contact with each other and positive electrodes are in contact with each other, and arranged such that a taking-out lead electrode smaller than negative or positive electrode surfaces are sandwiched between two negative electrodes in contact with each other or two positive electrodes in contact with each other, and the lead electrodes sandwiched between electrodes of different layers are arranged such that there is no region where all of the lead electrodes simultaneously overlap one another as viewed in a planar arrangement. There are a strip-shaped lead electrode and a linear lead electrode. Further, a conductive sheet forming the electrode is extended to also serve as the taking-out electrode, thereby making it possible to reduce the number of lead electrodes.

Stacked-type secondary battery

A multi-layer wiring board includes wiring layers stacked on a substrate with an insulating layer between each layer. A wire formed in the wiring layer consists of a first layer and a second layer to form a double layered structure. The first layer is made of a first conductive material and the second layer is made of a second conductive material having relative magnetic permeability of 10 or more and larger than that of the first conductive material. The characteristic impedance of the wire is adjusted to a value closer to 50 ohms than that of a wire which has the same thickness as of the wire with the double layered structure, and is made only of the first conductive material.

Multilayer wiring board with enclosed Ur-variant dual conductive layer

An apparatus includes a wiring base plate arranged on an upper side of a chuck top and having a wiring path connected to a tester, a probe card having a probe board spaced from the wiring base plate with a first surface thereof opposed to the wiring base plate and having a wiring path corresponding to the wiring path and probes provided on a second surface of the probe board to be connected to the wiring path and enabling to respectively contact connection pads of a semiconductor wafer on the chuck top, and an electric connector connecting the wiring base plate to the probe board by low heat conduction supporting members and decreasing heat conduction therebetween and electrically connecting the wiring paths.

Electric connecting apparatus

An apparatus includes a probe card having a probe board with a conductive path electrically connected to a tester and probes enabling to respectively contact connection pads of a semiconductor wafer on a chuck top and moving relatively to the chuck top, and an elastic heat conducting member arranged between a working surface of the chuck top or the semiconductor wafer on the working surface and the probe board. The elastic heat conducting member can abut on the working surface of the chuck top or the semiconductor wafer on the working surface and the probe board when the probes do not abut on the respective corresponding connection pads and is elastically deformable not to prevent abutment between the probes and the respective corresponding connection pads.

A probe card for an electric test of a device under test on a working table incorporating a heat source includes a circuit base plate including conductive paths connected to a tester, a probe base plate including conductive paths corresponding to the conductive paths and provided with probes connected to the conductive paths, and a heat expansion adjusting member bonded to the probe base plate, having a different linear expansion coefficient from that of the probe base plate to restrain heat expansion of the probe base plate, and constituting a composite body with the probe base plate. In a case where, when the device under test is at two measuring temperatures, the composite body is at corresponding achieving temperatures, expansion changing amounts of the device under test and the composite body under temperature differences between the respective measuring temperatures and the corresponding achieving temperatures are set to be approximately equal.

Probe card and method for manufacturing the same

A computer program generates a wire routing pattern that connects one driver with a plurality of receivers. The overlapping length of each vector pair, which consists of any two vectors headed from the driver to the receivers, is calculated. One vector pair that has the greatest overlapping length is selected. For the selected vector pair, three kinds of common nodes are created, each of which is used to make a common path part of the way to the receivers, to generate three kinds of renewed vector patterns. The operations are repeated and plural candidate routing patters are acquired. One candidate routing pattern having the smallest total wiring length is selected as the optimum routing pattern. If there exist plural patterns that have the same smallest total wiring length, one pattern can be selected that has the smallest one of the greatest. D-R path lengths.

Computer program and method for generating wire routing pattern

A method of manufacturing a multilayer wiring board is provided. A flat surface is formed on a surface of a multilayer wiring layer, and resistive material is deposited on the flat surface. The multilayer wiring board comprises a multilayer wiring layer on whose surface convexo-concave is formed, a dummy layer burying the convexo-concave, a resistance material layer made of an electrical resistance material deposited on the dummy layer and at an area going beyond the dummy layer, and a wire made of a conductive material deposited on the resistance material layer and ranging from the area going beyond the dummy layer to a part of the flat surface area of the dummy layer, wherein a resistive element is formed at an area of the resistance material layer that the wire does not reach.

Method for manufacturing a multilayer wiring board

A wiring path of a circuit board has a first vertical path portion penetrating the circuit board at its outer edge in its thickness direction and connected to a connector on one surface, a second vertical path portion penetrating the circuit board in its thickness direction and connected to the electric coupler on the other surface, and a lateral path portion connecting both vertical portions, and the second vertical path portion is formed within an arrangement area (S) of a reinforcing plate. One connecting end portion (electric coupler side) of the wiring path of the circuit board is disposed within the arrangement area (S) of the reinforcing plate. On the other hand, the other connecting end portion (probe side) of the wiring path of the circuit board is disposed to be dispersed in an arrangement area (S) wider than the arrangement area (S) of the reinforcing plate.

Electrical connecting apparatus

To be able to receive a laser beam having a predetermined intensity even if lengths of optical fibers differ, a laser beam transmitted from a counterpart of communication is received by a photodiode, an electric signal produced thereby is amplified by an amplifying unit and thereafter, a peak value of the signal is detected by a peak hold unit, a differential amplifying unit calculates a difference between an output signal from the peak hold unit and a reference level (Rx. Ref), forms a control signal based on the difference and outputs it to APC via a selector, APC controls an LD drive unit in accordance with an output from a photodiode where a portion of a laser beam emitted from LD is incident and the signal outputted from the differential amplifying unit, and the LD drive unit amplifies transmitted data (Tx. Data) in accordance with a signal outputted from APC thereby driving LD.

Optical signal communication apparatus and optical signal communication method

A transmission optical signal emitted from a laser diode is introduced in an S-polarized state to a polarization-reflection film formed on an inclined surface of a prism. This transmission optical signal is in a light quantity that is reflected by the polarization-reflection film to enter an optical fiber. With this configuration, an optical transmission-reception apparatus for a single-core bi-directional optical communication circuit enables an enhancement of the efficiency of introduction of the transmission optical signal into the optical fiber constituting the optical communication circuit so that a sufficient performance and reliability of the optical communication circuit is realized without increasing the light quantity emitted from the laser diode which outputs the transmission optical signal.

Optical transmission-reception apparatus

In an LSI package, terminal resistance elements are formed of resistive paste which, consisting of a mixture of fine powder of either oxidized metal or carbon and fine powder of glass, is buried and sintered in a ceramic wiring board in the direction to penetrate it. Front side wiring, connecting the parts of the terminal resistance elements exposed on the front face of the ceramic wiring board to input/output circuits of the LSI chip to be mounted on the front face of the ceramic wiring board, is formed on the front face of the ceramic wiring board and in the top layer of the ceramic wiring board. Back side wiring, connecting the parts of the terminal resistance elements exposed on the back face of the ceramic wiring board to a voltage clamp wiring network, is formed on the back face of the ceramic wiring board.

LSI package and manufacturing method thereof

Growing community of inventors

Tokyo, Japan

Tatsuo Inoue