Kabushiki Kaisha Toshiba

Tatsuo Ikawa

Shigeo Ohshima

Haruki Toda

Tohru Furuyama

Shigeyoshi Watanabe

Naoki Matsumoto

Katsushi Nagaba

Shigeo Oshima

Masao Kudou

Naoyuki Mine

There is provided a semiconductor memory device having output ports for serially accessing memory cells connected to a plurality of select lines, comprising: a decode counter adapted to be supplied with an initial value to count up to generate a plurality of counter address signals to output first decode signals obtained by decoding the counter address signals; and a serial decoder adapted to be supplied with the first decode signals respectively outputted from the decode counter to decode them to output second decode signals for selectig any one of the select lines.

Semiconductor memory device

A multiport memory comprises a pair of memory cells, at least a pair of bit line and a pair of word lines on a random access port side. One of the memory cell is connected to one bit line and one word line and the other memory cell is connected to the other bit line and the other word line. A pair of data lines which are respectively connected to load elements are also provided in the random access port side of the multiport memory. A first switch circuit is connected between the pair of bit lines and the pair of data lines. On a serial access port side, a data register is connected between the pair of bit lines to receive data transmitted through the pair of bit lines. A second switch circuit for transmitting data is connected between the pair of bit lines and the data register. A control circuit opens the first switch circuit, before closing the second switch circuit to transmit data stored in the memory cells to the data register.

Multiport memory

A data output circuit for a semiconductor integrated circuit device for outputting a data signal in sync with an output enable signal externally supplied, including: a comparing circuit for comparing a first data signal being outputted presently with a second data signal to be outputted next, when the data signal to be outputted is changed, and judging whether the first and second data signals are the same or different; a first output circuit for temporarily turning off output transistors and outputting the second data, if the comparing circuit judges that the first and second data signals are different; and a second output circuit for outputting the second data signal without turning off all the output transistors, if the comparing circuit judges that the first and second data signals are the same.

Data output circuit for semiconductor integrated circuit device

There is disclosed a semiconductor integrated circuit device comprising: at least two first power supply voltage leads provided outside a chip adapted to be supplied with a first power supply voltage, e.g., VSS and a second power supply voltage, e.g., VCC and supplied with said first power supply voltage; at least two first power supply voltage terminals provided inside the chip, and connected to respective different ones of the first power supply voltage leads; an external input circuit adapted so that a signal is inputted from the outside of the chip, and connected to at least any one of first power supply voltage terminals; and an internal circuit adapted so that the signal is inputted from the external input circuit, and connected to one which is not connected to the external input circuit of the first power supply voltage terminals. Further, this semiconductor integrated circuit device may further comprise at least two second power supply voltage terminals provided inside the chip, and connected to respective different ones of the second power supply leads.

Semiconductor integrated circuit device

A semiconductor memory device having: a RAM port for randomly accessing a memory cell array having memory cells disposed in matrix; a SAM port for serially accessing data of one row of the memory cell array; a mode switching unit for switching the operation mode of the SAM port between an ordinary data output mode and a test mode, upon externally receiving a mode switching signal; and an address pointer outputting unit for outputting an address pointer of the SAM port when the operation mode is switched to the test mode by the mode switching unit.

The disclosed semiconductor memory comprises a random access memory port, a serial access memory port, a data transfer gate formed between the two ports, and in particular a test signal generating circuit for generating a test signal to the data transfer gate to close the gate so that data stored in the serial access memory port can be read to outside, without transferring data from the random access memory port to the serial access memory port. Therefore, it is possible to discriminate an erroneous operation caused when data are read from the serial access memory port from that caused when data are transferred from the random access memory port to the serial access memory port.

Multiport memory with test signal generating circuit controlling data

A function selection circuit includes a first signal generating circuit for generating a plurality of first signals corresponding to each of all combinations of a plurality of input signal states; and a second signal generating circuit for selecting a plurality of logical sums of combinations of the plurality of first signals and generating a second signal corresponding to each of the plurality of logical sums which selectively activates an operation function indicated by a truth table.

Function selector circuit

Memory cells disposed in a matrix are divided into a plurality of blocks. Each block is constructed of n (n is a positive integer larger than 2) memory cell columns. One block is selected by one column address. One memory cell column in the n memory cell columns in a selected block is selected by a first gate. One memory cell column in the n memory cell colunns in a selected block is selected by a second gate. One memory cell in a selected memory cell column is selected by a row address. The data in a selected memory cell are stored in a register and output therefrom.

This invention provides a multiport memory including a storage section A having bit lines BL and BL, a word line WL, a data transfer gate .phi.DT, and a dynamic memory cell Cs, and a serial port B having a serial access function in a column direction of the storage section, wherein the memory includes a circuit for disabling a word line signal WL for selecting one word line under the conditions that a row address strobe signal RAS is raised in a transfer cycle in which data held by the memory cell is transferred to the serial port, and that the data transfer to the serial port is completed by the data transfer gate .phi.DT.

Multiport memory with improved timing of word line selection

A signal externally supplied to determine the operation mode is supplied to a first buffer circuit. A CAS signal is supplied to a second buffer circuit. The signals whose levels are converted by the first and second buffer circuits are supplied to a mode selection circuit. The operation of the mode selection circuit is controlled by a RAS signal, and it latches and outputs a mode selection signal based on the outputs of the first and second buffer circuits. An externally supplied address signal and an address signal formed in the device are supplied to address buffer circuit. The address buffer circuit selects one of the received address signals based on the RAS signal anad the mode selection signal output from the mode selection circuit. A selected one of the address signals is supplied to a word line selection/driving circuit. When a mode other than the auto-refresh mode is specified, the mode setting signal is set up before the RAS signal is activated. The set-up allowance time with respect to the activation timing of the RAS signal is set to be larger than the minimum value of the set-up allowance time of the external address signal. The mode setting signal is latched by the mode selection circuit when the RAS signal is activated. The latched signal is used to select and control the operation mode.

Operation mode setting circuit for dram

A dynamic memory having pairs of bit lines. A sense amplifier is connected between each pair of bit lines for detecting data from the potential difference between these bit lines. The memory further comprises first and second pair of dummy word lines. A capacitor is coupled between the first of each pair of bit lines, on the one hand, and the first pair of dummy word lines, on the other. Similarly, a capacitor is coupled between the second of each pair of bit lines, on the one hand, and the second pair of dummy word lines, on the other. A first dummy word line driver is connected to the first pair of dummy word lines, for generating a reference potential in the first of each pair of bit lines. A second dummy word line driver is connected to the second pair of dummy word lines, for generating a reference potential in the second of each pair of bit lines. The memory also has a selection circuit for selecting either the first or second dummy word line driver. During a precharging period, either dummy word line driver sets both pairs of dummy word lines at a precharging potential. During a data-reading period, the dummy word line driver selected by the selection circuit sets the dummy word lines at a high potential and a low potential, respectively, and the dummy word line driver selected by the selection circuit sets both dummy word lines at a precharging potential.

Dynamic memory

A semiconductor memory device has N sense amplifiers each having first and second input terminals, N first memory cells, N second memory cells, N first bit lines each of which is connected to the first memory cells of the same column and connected to the first input terminal of one of the sense amplifiers, and N second bit lines each of which is connected to the second memory cells of the same column and connected to the second input terminal of one of the sense amplifiers. The first memory cells are formed in a first memory cell area and the second memory cells are formed in a second memory cell area arranged adjacent to the first memory cell area and on the same side as the first memory cell area with respect to the sense amplifiers.

Growing community of inventors

Mitaka, Japan

Tatsuo Ikawa