Sanyo Electric Co., Ltd.

Other

Kabushiki Kaisha Media Marketing Network

Tatsuo Hiramatsu

Yoshikazu Tomida

Kazuhiro Kimura

Shigeaki Hayashibe

Hironori Mitoh

Toshiyuki Ozawa

Masahiro Sata

Hiromichi Suzuki

Hiroshi Nakajima

Katsunori Hirase

Masahiro Seto

Makoto Ozone

Ryuuji Yoshihara

Makoto Okada

Tadashi Etoh

Hideki Kasamatsu

Eiji Nakayama

Seiji Suzuki

Noriaki Minami

Naruto Nishimura

Hiroaki Takagi

Kanji Nakano

A reconfigurable circuit of reduced circuit scale. The reconfigurable circuit of the present invention comprises a plurality of ALUs capable of changing functions. The plurality of ALUs are arranged in a matrix. At least one connection unit capable of establishing connection between the ALUs selectively is provided between the stages of the ALUs. This connection unit is not intended to allow connection between all the logic circuits in adjoining stages, but is configured so that the logic circuits are each connectable with only some of the logic circuits pertaining to the other stages. The connection limitation allows a reduction in circuit scale.

Reconfigurable circuit with a limitation on connection and method of determining functions of logic circuits in the reconfigurable circuit

A data flow graph processing method divides a program describing target operations into two or more subprograms and converts each of the two or more subprograms into a data flow graph (DFG) representing dependency in execution between operations carried out in sequence. Also generated is flow data indicating the order of execution of DFGs corresponding to respective subprograms. DFGs are converted into configuration data and the flow data is converted into control data.

Data flow graph processing method and processing apparatus provided with reconfigurable circuit

Image data scaled by a scaling circuit and then multiplied by a weighting factor by a weighting factor multiplier circuit and an on-screen-display (OSD) data multiplied by a weighting factor by a weighting factor multiplier circuit and then scaled by a scaling circuit are combined together by a combining circuit to generate composite image data and the resultant composite image data is accordingly reproduced.

Image data output device and receiving device

A prefix corresponding to a data block at the head of each of data groups in data of a layer of a received FM multiplex broadcast program and data of a layer of the received FM multiplex broadcast program are stored in first storage means. When a data retention command is entered, the data of the layer is produced on the basis of the prefix and the data of the layer which are stored in the first storage means, and the produced data of the layer is retained in second storage means as versatile recording and reproducing data.

FM multiplex broadcasting receiver and storage of received data in FM multiplex broadcasting receiver

The credit card information management system checks the creditability of a credit card intended to be used for purchase of goods or service by using the card information owned by member stores of credit companies. A host computer of the card management center outputs information regarding the validity or invalidity of a credit card of a customer member of a credit company as card information, a transmission facility wirelessly transmits digital data of the card information. A receiving facility of a member store receives radio signals of the card information and checks whether or not there is any missing of data. If any missing occurs, a transfer of the missed data is requested to the host computer. A terminal computer extracts only the card information necessary for one's own store from the data outputted by the host computer and data outputted in response to the transfer request and stores the same in memory, and the terminal computer outputs judgement of validity or invalidity of a credit card inputted into a card reader.

Credit card information management system

A second random number generator (102) sets a scramble key data included in a transmitted/received data to an initial value, and it generates predetermined second random numbers. A first random number generator (101) generates first random numbers from the second random numbers supplied by the second random number generator (102). The generation of the first random numbers by the first random number generator (101) is controlled by an output from a first control circuit (103). Since the output from the first control circuit (103) is changed in accordance with a service identification code SI, the first random numbers generated from the first random number generator (101) are changed. The first random numbers are input to a gate circuit (105) via a second control circuit (104). The second control circuit (104) inhibits the output of the first random numbers in accordance with the SI value. In such a manner, scrambling or descrambling is controlled in the gate circuit (105).

Data processor for FM multiplex broadcast

A system for managing sales of goods for vending machines includes a goods control center, a plurality of vending machines, and terminal computers equipped in the respective vending machines. The goods control center includes a host computer for preparing digital data signals as control instructions, and a frequency moderation sub-carrier broadcasting facility as a transmission facility for outputting the digital data signals. Each vending machine has a receiving facility for receiving the digital data signals from the goods control center, and a responding facility. Each terminal computer receives the digital data signals and selectively extracts the digital data as the control instructions necessary for the vending machine to thereby store the digital data necessary for the vending machine in a memory. Each terminal computer controls the vending machine on a basis of the control instructions stored in the memory, obtains goods market information of the vending machine, and outputs the goods market information to the responding facility for reporting the information to the host computer at the goods control center.

System for managing sales of goods for vending machines

An FM multiple radio broadcasting receiver includes a data group number and data packet number derivation circuit by which a data group number and a data packet number included in a prefix of FM subcarrier data are derived. A first random number generator generates a first random number on the basis of the data group number, the data packet number and scramble key data which is outputted from a scramble key generation circuit, and sets the first random number in a second random number generator as its initial value. Therefore, it is possible to appropriately scramble or descramble with using packet structure of the FM subcarrier data.

Method for scrambling and/or descrambling FM subcarrier data

A scrambling key is generated from demodulated and error-corrected FM demodulation data for use in descrambling. During this process, if error correction has not been normally conducted to an object data packet, a subsequent descrambling operation is not executed to that data packet. In addition, a descrambling operation is not carried out if the object data packet is a parity packet.

Data processing device for FM multi-channel broadcasting

In a packet analyzing circuit, first and second key data are detected and stored in respective first and second key data registers. First and second key generation circuits generate first and second keys from the first and second key data. An exclusive OR operation is carried out to both keys so as to generate a scrambling key. Using the scrambling key as an initial value, a random number generator generates a PN code used for scrambling, so that scrambled data is descrambled by adding the PN code to the data. The first key generation circuit, which receives a control signal CON from a timing generation circuit, is controlled by the control signal CON such that a scrambling key is generated only when the random number generator needs an initial value.

Descrambling device

In a decoding processing circuit of a digital signal receiver, a first comparison circuit detects that a prefix of packet data is inputted in a shift register on the basis of a count value of a counter circuit. In response to the result of detection, a pseudo-random binary sequence generation circuit outputs a pseudo-random binary sequence on the basis of a data group number and a data packet number outputted from the shift register and key data previously extracted by a key data fetch circuit. When a second comparison circuit detects that block data in the data packet is inputted in the shift register, an exclusive OR circuit exclusively ORs the pseudo-random binary sequence with receive data, so that decoded data is inputted in the shift register.

Digital signal receiver capable of receiving data encrypted and

A bi-phase signal is output from BPSK demodulator; by a pair determining circuit and a clock reproducing circuit, a clock signal corresponding to a former half bit of two half bits constituting a data pair of the bi-phase signal is reproduced; a carrier pulse immediately following the clock signal is generated by a carrier extracting circuit; using the carrier pulse and a carrier pulse obtained by delaying the pulse signal by a half bit period as a sampling clock, the bi-phase signal is subjected to AD conversion by AD converting circuit; two AD converted data values different in time are input to a subtraction circuit, and a result of subtraction between data pairs of bi-phase signals is obtained; thus sign of a bi-phase signal is determined.

Decoding circuit for bi-phase BPSK signal having a high noise immunity

A costas loop includes a comparator, and a BPSK-modulated signal which is converted into a binary signal by the comparator is latched by a D-FF according to an oscillation signal from a VCO. An output of the D-FF becomes a demodulated signal. On the other hand, a phase-difference between the BPSK-modulated signal and the oscillation signal is detected by a phase-comparator, and the phase-difference is applied to the VCO via a loop filter. An oscillation frequency of the VCO is thus controlled according to a phase-comparison result.

Costas loop and data identification apparatus

A spread spectrum communictdion system includes a transmitter and a receiver, and an on-off keying signal is inputted to the transmitter. A carrier signal is modulated by the on-off keying signal, and a spread spectrum signal is produced by multiplying a modulated signal by a first PN code which is repetition of 3-bit data. The spread spectrum signal is transmitted through a transmission antenna. In the receiver, a second PN code which is repetition of 4-bit data larger than the first PN code by 1 bit is generated. Therefore, a phase of the second PN code becomes coincident with a phase of the first PN code every 12 bits. Then, a spread spectrum demodulation is performed by multiplying a received spread spectrum signal by the second PN code to reproduce the carrier signal being modulated by the on-off keying signal. The on-off keying signal is restored by envelope-detecting a reproduced carrier signal.

Spread spectrum communication system

A spread spectrum signal demodulation circuit includes a multiplier which multiplies an input spread spectrum signal by a demodulation PN code, and a demodulation PN code generator generates the demodulation PN code by utilizing an oscillation signal from a VCO as a clock signal thereof. An output of the multiplier is given to a bandpass filter and an output of which is integrated by an integration circuit. A first integrated value for a first time is compared with a second integrated value for a second time later than the first time and, in accordance with a comparison result, a frequency of the oscillation signal of the VCO is changed so that the demodulation PN code is synchronized with a modulation PN code included in the input spread spectrum signal.

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Kadoma, Japan

Tatsuo Hiramatsu