Hitachi, Ltd.

Hitachi Software Engineering Company, Ltd.

Hitachi Information Technology Co., Ltd.

Tatsuki Ishii

Katsuyoshi Suzuki

Tetsuo Sasaki

Hachidai Nagase

Tutomu Itoh

Yousuke Nagao

Kenji Shigeoka

Tomio Taniguchi

Hirotake Tokuyama

Tooru Hiyama

Misao Takimoto

Makiko Iwanabe

Yoshihiro Iwai

Itaru Matsumoto

A delay diagnosis method is proposed that can avoid design steps from being retraced or repeated uselessly due to defective delay when we design a semiconductor integrated circuit including a plurality of blocks. This delay diagnosis method has the steps of inputting logic information and floor plan information, finding the number of start points connected to the end point of a path from the logic information, computing the logic stage number of the path from the number of start points, finding block-to-block distances from the floor plan information, computing intra-block delays from the logic stage number and gate unit-value delays, computing inter-block delays from the block-to-block distances and routing unit-value delays, and diagnosing if the delay of the path after logic synthesis can be converged within a target path delay from the relation among the computed intra-block delays and inter-block delays and the target path delay.

Delay diagnosis method for semiconductor integrated circuit, computer program product for diagnosing delay of semiconductor integrated circuit and computer readable recording medium recording program thereon

Each flip-flop-to-flip-flop path delay and a target machine cycle obtained in the stages of physical design and packaging design are used as input, and with respect to a path in which the path delay is not less than the target machine cycle, a closed loop including the path is extracted, and the timing of a clock signal of each flip-flop is adjusted so as to permit data transmission along the closed loop in a required cycle-number. At this time, a path along which data transmission is impossible in the target machine cycle or a closed loop including the path is listed in order to be modified. As methods of supplying a clock signal to each flip-flop, a plurality of methods different in the adjustable range of clock timing are combined and used.

Design method and system for achieving a minimum machine cycle for semiconductor integrated circuits

A control device and a storage device are provided. The storage device has a clock signal file for determining a delay reference value for a path, and a logic information file for holding description of elements in the path. The control device refers to the clock signal file and the logic information file to determine an combination of the emitter-follower current and the value of the current-switch current of a certain element in the path.

System and method for optimizing delays in semiconductor circuits

An interconnection path layout in a circuit structure having terminals arranged in rows, such as a semiconductor integrated circuit. Paths are first assigned to selected obstruction-free terminal pairs to be interconnected, and then bypasses are assigned to the remaining obstruction-existing terminal pairs to be interconnected. This minimizes the occurrence that the terminal pairs are left un-interconnected. Also, longer vertical paths are assigned to selected terminal pairs with priority. This prevents the reserved paths from becoming obstructions to vertical paths which are later assigned to selected terminal pairs.

Circuit structure, semiconductor integrated circuit and path routing

A method of automatic wiring in a semiconductor integrated circuit device having four or more wiring layers, with the lowest layer being a terminal layer, is intended to overcome the prior art problem in which lower layers are mostly used for wiring and upper layers are not used efficiently. The method is designed to assign longer lines to upper layers distant from the terminal layer, and upper layers can have increased wiring densities with minimal numbers of lines, bends and through holes, thereby using upper layers efficiently.

Method of automatic wiring in a semiconductor device

For signal lines to be connected from an LSI device or a module including a plurality of LSI devices as a mounted part via input/output pins thereof to external devices, pin assignment positions are determined as follows. The signal lines are classified into groups depending on attributes thereof. Priority levels are determined for the resultant groups according to the attributes. Based on relationships with respect to arrangement positions of the mounted parts to be connected to the signal lines, provisional pin positions are computed so as to minimize wiring lengths between the mounted parts. The input/output pins are assigned to the provisional pin positions for each signal line group in an order of the priority levels.

Input/output pin assignment method

A novel wiring method for multilayered semiconductor integrated circuits is disclosed. For example, a semiconductor integrated circuit of a 6-layered wiring structure can be formed with a first layer covered with gates, a second layer, a third layer, a fourth layer and a fifth layer making up logic wiring layers, and a sixth layer making up a power layer. Lattice-shaped wires are formed in a longitudinal direction on the second layer and the fourth layer, and in a lateral direction on the third layer and the fifth layer. The second layer forming the bottom layer and the fifth layer forming the uppermost layer, or a combination of the second layer and the fifth layer of a general wiring structure are used as main layers of wires requiring consideration of signal transmission delay time.

Wiring method for semiconductor integrated circuits

For the purpose of satisfying placement constraint prescribed by design rule data, a region to which a plurality of circuit elements appertain is displayed in such a way that this region is moved to such a position as to environ a part of the circuit elements and at the same time is superposed on a layout graph thereof. The placement of the circuit elements is updated such that some elements placed outside the foregoing region among all the circuit elements are made to enter this region.

Growing community of inventors

Tokyo, Japan

Tatsuki Ishii