Renesas Electronics Corporation

Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Systems Co., Ltd.

Semiconductor Technology Academic Research Center

Hitachi Tohbu Semiconductor, Ltd.

Other

Hitachi Ulsi Engineering Corp.

Renasas Technology Corporation

Tatsuji Matsuura

Hideo Nakane

Takaya Yamamoto

Keisuke Kimura

Eiki Imaizumi

Yuichi Okuda

Takashi Oshima

Kunihiko Usui

Hiroki Nakajima

Yasutoshi Aibara

Masumi Kasahara

Toshihito Habuka

Toshiro Tsukada

Naoto Inokawa

Katsumi Yamamoto

Koichi Yahagi

Hirokazu Miyagawa

Takanobu Anbo

Seiichi Ueda

Ryuichi Ujiie

Masao Hotta

Kiyoharu Ozaki

Takahiro Miki

Koichi A Ono

Takayuki Tsukamoto

Mitsuru Hiraki

Koichiro Mashiko

Masaru Kokubo

Yasuhiko Sasaki

Koichi Seki

Toru Baji

Shinya Ohba

Akira Abe

Masaki Noda

Kazuaki Hori

Haruo Kobayashi

Hiroshi Sato

Kenichi Hase

Atsushi Motozawa

Teruaki Odaka

Toyokazu Hori

Kouichi Yahagi

Tetsuo Matsui

Naoki Yada

Hiroshi Nogami

Kazuya Shimizu

Yoshitaka Jingu

Masato Kaneta

Katsumi Osaki

Katsuyoshi Yagi

Junya Kudo

Junya Kudoh

Oshima Takashi

Yasuhiko Sone

Akihiro Kitagawa

Imaizumi Eiki

Hisashi Okazawa

Kenji Toyota

Yuichi Nakatani

A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.

Passive amplification circuit and analog-digital convertor

To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.

Electronic system and operating method thereof

A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.

Semiconductor integrated circuit device

A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.

Semiconductor device having Analog-to-Digital Converter with gain-dependent dithering and communication apparatus

Provided is a semiconductor device that is capable of performing background calibration during a reception operation without adversely affecting reception characteristics. During a reception operation, the semiconductor device detects a timing at which an invalid received signal occurs upon a gain change or a reception channel change and performs background calibration at the detected timing. In this instance, as the received signal is invalid, performing the calibration does not further decrease the substantial accuracy of reception. Moreover, an unnecessary signal component, which would arise when the background calibration is performed at fixed intervals, will not be generated as far as the background calibration is performed at random timing.

Semiconductor device and adjustment method therefor

Semiconductor device having analog-to-digital converter with gain-dependent dithering and communication apparatus

A semiconductor integrated circuit device having A/D converters for converting, by means of digital correction processing, analog input signals into digital signals is reduced in area. The semiconductor integrated circuit device has a first A/D converter and a second A/D converter. In a first mode, a first test signal is inputted to both the first and second A/D converters, and a first correction coefficient for the first A/D converter and a second correction coefficient for the second A/D converter are calculated. In a second mode, the first A/D converter converts a first analog signal into a first digital signal by subjecting the first analog signal to a first digital correction processing and the second A/D converter converts a second analog signal into a second digital signal by subjecting the second analog signal to a second digital correction processing.

To improve resolution of a built-in A/D converter by reducing the area occupied by a chip of the built-in A/D converter in a semiconductor integrated circuit that is mounted in an on-vehicle millimeter wave radar device and which incorporates an A/D converter and an MPU. In the semiconductor integrated circuit, a plurality of reception signals of the radar device is A/D-converted by a single digital correction type A/D converter. The digital correction type A/D converter of the single A/D converter is a foreground digital correction type A/D converter that sequentially A/D-converts the reception signals output from a multiplexer of a receiving interface. The single A/D converter includes a pipeline type A/D converter having a plurality of cascade-coupled converters. The semiconductor integrated circuit comprises a correction signal generating unit, a digital correction D/A converter, and a digital correction unit for digital correction.

Semiconductor integrated circuit and method of operating the same

An integrated circuit is equipped with a reception mixer and a signal generator. A multistage delay circuit generates a plurality of clock pulses in response to a reception carrier signal. A phase detection unit detects differences between a voltage level of a specific clock pulse and voltage levels of a predetermined number of clock pulses generated prior to the specific clock pulse to thereby detect a predetermined phase of the specific clock pulse. A selector of a clock generation unit outputs a plurality of selection clock pulse signals respectively having a plurality of phases from the clock pulse signals. A first signal synthetic logic circuit performs logical operations on the selection clock pulses to thereby generate local signals supplied to the reception mixer.

Semiconductor integrated circuit and operating method thereof

A sequential comparison-type analog-to-digital converter (ADC) that has improved precision and which is capable of high-speed operation is disclosed, the analog-to-digital converter comprising a digital-to-analog converter that outputs a plurality of different reference analog signals according to a multibit digital signal, a plurality of comparators that compare an input analog signal with the plurality of reference analog signals, and a sequential comparison control circuit that changes bit values of the multibit digital signal in order from higher bits so that at least one of the plurality of reference analog signals becomes closer to the input analog signal and decides the bit values in order from higher bits based on the comparison results and at the same time, correcting the decided higher bit values, wherein the sequential comparison control circuit decides the bit values of the multibit digital signal down to a predetermined bit based on the comparison results of the plurality of comparators and at the same time, correcting the bit values, and decides the bits lower than the predetermined bit based on the comparison result of one of the plurality of comparators.

Analog-to-digital converter

A D.C. offset canceling and gain adjusting techniques permitting completion of correction of D.C. offsets and gain adjustment of amplifiers for amplifying reception signals in a radio communication system are provided. A communication semiconductor integrated circuit has a plurality of low-pass filters and variable gain amplifiers which are alternately connected in multiple stages, and high gain amplifier circuits for amplifying reception signals to a predetermined amplitude level. Offset cancellation values are generated by detecting D.C. offsets of amplifiers for amplifying reception signals according to a set gain, and stored into a memory, and read out of the memory to cancel the D.C. offsets of the amplifiers when starting reception and altering the gain. Gain setting in a high gain amplifying section is accomplished using rough and precise settings.

Communication semiconductor integrated circuit, radio communication system, and adjustment method of gain and offset

A TDC circuit having a small scale circuit and high resolution is disclosed, which is a time-to-digital converter that detects a phase with respect to a reference clock of a signal to be measured, comprising a first delay line in which a plurality of first delay elements with a first delay amount is connected in series, a second delay line group that is connected to a plurality of connection nodes of the first delay line or an input node in the first stage and in which at least one or more second delay elements with a second delay amount different from the first delay amount are connected in series, a plurality of judgment circuits that judge whether the changing edge of the signal to be measured is advanced or delayed with respect to the changing edges of a delayed clock output from the first delay element and the second delay element, and an operation circuit that calculates a phase with respect to the reference clock of the changing edge of the signal to be measured from the judgment results, wherein a difference between the first delay amount and the second delay amount is smaller than the first delay amount and the second delay amount.

Time-to-digital converter

Growing community of inventors

Kanagawa, Japan

Tatsuji Matsuura