Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Tatsuhiro Suzumura

Kiwamu Watanabe

Akihiro Oue

Shuji Michinaka

Satoshi Takekawa

Takaya Ogawa

Yoshinori Shigeta

Masashi Jobashi

Hiromitsu Nakayama

Yoshihisa Kojima

Tokumasa Hara

Yohei Hasegawa

Yoshiki Saito

Hiroyuki Moro

Akira Yamaga

Kunihiko Yahagi

Hisae Kita

According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.

Memory system

Memory system utilizing a page buffer for prioritizing a subsequent read request over a pending write

According to one embodiment, a memory system includes a nonvolatile memory, a command managing unit, a command issuing unit, a data control unit and a command monitoring unit. The command issuing unit issues a command received by the command managing unit to the nonvolatile memory. The data control unit controls a reading or writing of data to the nonvolatile memory. The command monitoring unit monitors the command managing unit and outputs a receipt signal to the data control unit when the command managing unit receives the command. The data control unit interrupts the reading or writing when receiving the receipt signal, issues the command from the command issuing unit to the nonvolatile memory, and resumes the reading or writing after issuing the command.

Memory system including nonvolatile memory

A memory controller includes a memory interface that has multiple channels and carries out writing into a nonvolatile memory through each of the channels, a data buffer, an ECC (error correcting code) encoder for applying an error correction encoding processing on write data which are to be written into the nonvolatile memory to generate ECC data, a channel allocation part for allocating the channels to the write data and the ECC data based on a write data format of the nonvolatile memory, a write data reception processing part that stores the write data in the data buffer and outputs the write data to the ECC encoder, and a channel scheduler for transferring the write data stored in the data buffer and the ECC data to the channels of the memory interface as allocated by the channel allocation part.

Memory controller, memory system, and memory write method

According to one embodiment, a semiconductor device includes a storing section that stores a setting state that is one of a first connecting state in which another end of a first outbound system bus is connected to an outbound output terminal and another end of a first inbound system bus is connected to an inbound output terminal, and a second connecting state in which another end of a second outbound system bus is connected to the outbound output terminal and another end of a second inbound system bus is connected to the inbound output terminal; and a control section that controls an outbound path switching section and an inbound path switching section based on the setting state so as to assume one of the first connecting state and the second connecting state.

Semiconductor device controlling outbound and inbound path switching sections based on a setting state and controlling method thereof

A stream transmitting section outputs encoded stream data. A division instructing section generates dividing point information that designates a dividing point of the encoded stream data. A parallel stream transmitting section divides stream data that is output by the stream transmitting section and side information necessary for decoding from halfway along the stream that is extracted based on the stream data into a predetermined number of parts at dividing points designated by the dividing point information, performs parallelization thereof, and transmits data obtained as a result thereof to a stream decoding section on a receiving side.

Image information transmission apparatus

The image decoding apparatus and the image decoding method according to one aspect of the present invention have a configuration for storing an image decoded in the past as a reference picture into a frame memory, in a field structure in which top lines in the reference picture are stored in a top area and bottom lines in the reference picture are stored in a bottom area, in order to use a part of the image decoded in the past as a reference block in a picture being presently decoded; and selectively copying and storing an uppermost top line or an uppermost bottom line in the reference picture to areas on the uppermost top line and the uppermost bottom line in the reference picture in the top area and the bottom area in the frame memory, and selectively copying and storing a lowermost top line or a lowermost bottom line in the reference picture to areas under the lowermost top line and the lowermost bottom line in the reference picture in the top area and the bottom area in the frame memory.

Image decoding apparatus and image decoding method

A picture processing apparatus includes a decoder configured to decode encoded data to generate a decoded picture. A picture memory has a plurality of banks each containing a plurality of pages to which row addresses are assigned, and is configured to store the decoded picture. A bank selector is configured to divide the decoded picture into a plurality of blocks, and to select a page of a different bank as a write location for a block adjacent in at least one of either a horizontal direction or a vertical direction. A write controller is configured to write pixel data of pixels occupying even lines of each of the blocks, and pixel data of pixels occupying odd lines of each of the blocks in a column address direction of each of the page in an alternating manner.

Picture processing apparatus, semiconductor integrated circuit, and method for controlling a picture memory

An image decoding apparatus having: a table selection controller configured to output a syntax selection signal which selects one of a prefix, a suffix, and a syntax; a variable length code decoding device configured to receive a bit stream, the syntax selection signal, and a suffix length, and, by using data contained in the bit stream and the suffix length, simultaneously decode the prefix and the suffix and output the result if the syntax selection signal selects the prefix 1 and the suffix, and decode the syntax and output the result if the syntax selection signal selects the syntax; a level formation device configured to receive the decoded prefix, the decoded suffix, and the decoded syntax, and form and output a level; and a suffix length updating device configured to receive the decoded prefix, the decoded suffix, and the decoded syntax, and update the suffix length.

Image decoding apparatus and decoding method

An image coding apparatus includes a variable length coding section, an arithmetic coding section and a common buffer memory. The variable length coding section inputs image data and outputs a binarized code sequence applied with variable length coding. The arithmetic coding section applies arithmetic coding to the binarized code sequence outputted from the variable length coding section. The common buffer memory transmits and receives data between the variable length coding section and the arithmetic coding section.

Image coding apparatus and method thereof

When a combination between a plurality of FIFO memories and a variable length coding table is used, a load generated by an increase in number of FIFO memories serving as output destinations of a codeword length output from the variable length coding table when the codeword length is output is reduced. A variable length code decoding apparatus includes an input unit which receives variable length coding data, a plurality of FIFO memories which store the variable length coding data and output or update the variable length coding data on the basis of a codeword length of the variable length coding data, a FIFO input selecting unit which outputs the variable length coding data to one of the plurality of FIFO memories, a variable length coding table storing unit which stores a variable length coding table representing a relationship between the variable length coding data, the codeword length and a decoding value, reads the variable length coding data stored in one of the plurality of FIFO memories, and compares the read variable length coding data with the variable length coding table, a table selecting unit which determines the codeword length and the decoding value on the basis of a comparison result of the variable length coding table storing unit, and outputs the determined codeword length to one of the plurality of FIFO memories, and a control unit which selects one of the plurality of FIFO memories as a destination FIFO memory, reads the variable length coding data from the input unit or one of the unselected FIFO memories, and controls the FIFO input selecting unit such that the read variable length coding data is output to the selected FIFO memory.

Variable length code decoding apparatus and variable length code decoding method

A system for decoding a variable-length codeword includes a buffer circuit storing the codeword, a detection circuit detecting the number of bits of a prefix portion of the codeword by use of a detection table while updating the codeword, an extraction circuit extracting a codeword of a suffix portion of the codeword based on the number of bits of the prefix portion while updating the codeword, and a first decoding circuit decoding the codeword base on the number of bits of the prefix portion and the codeword of the suffix portion.

System and method for decoding a variable-length codeword while updating the variable-length codeword

A logic circuit comprising a flip-flop chain circuit which is utilized in a scan test of a combinational circuit, the flip-flop chain circuit including a plurality of flip-flops each of which is provided with a selector.

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Kanagawa, Japan

Tatsuhiro Suzumura