International Business Machines Corporation

Tatchi Placido Lay

William Kress Bodin

Brien H Muschett

Cuong Huu Tran

James Gordon Wilkinson

Allen Justin Ramlow

Susan Yee

David Michael Hyde

Geoffrey Owen Blandy

Barry Alan Feigenbaum

Jonathan Mark Wagner

Gareth Christopher Matthews

Colin Victor Powell

Allen M Gilbert

Glenn T Puchtel

Mark Allen Fiechtner

Ivan Lomelli

Darren Mark Miclette

David Andrews Kerr

John Monroe Blackmon

Dung Huu Tran

Paul R King

Jeffrey Thomas Galea

The invention relates to a computer in which an image of the operating system is maintained in a secondary memory. This memory is either powered from a source independent of the main memory, or is non-volatile in nature. When the computer is reinitialized, the loader software that normally builds the operating system from components instead checks the secondary memory for the presence of an operating system image. If such an image is detected, the loader transfers the image from the secondary memory to the primary memory and transfers control of the computing system to the image of the operating system now in the primary memory. If no image is detected, the loader operates in a standard fashion. Additionally, a complete system image may be stored in the secondary memory. This would include the contents of the primary memory, the contents of the virtual memory, and the system state. As such, a preexisting version of an operational computing system may be directly loaded at boot time.

Method for fast reinitialization wherein a saved system image of an operating system is transferred into a primary memory from a secondary memory

A method and apparatus for executing and debugging programs in a data processing system. The data processing system includes a first dispatch table, wherein the dispatch table is located at a dispatch table address and wherein the dispatch table includes addresses to routines executed for bytecodes. A second dispatch table is provided in which the second dispatch table includes addresses to routines for analyzing a program and addresses to the routines executed for bytecodes. The data processing system includes an interpreter, wherein the interpreter accesses a dispatch table located at the dispatch table address to process bytecodes. The first dispatch table is saved in response to a request to analyze a program. The second dispatch table is copied to the dispatch table address in response to saving of the dispatch table.

Method and apparatus for dynamic swappable bytecode loop in java virtual machines

A method and system are disclosed which may be utilized to generate a simultaneous presentation within a data processing system of video data within multiple windows supported by different graphic user interfaces. Each graphic user interface is coupled to a separate display device driver. Window movements including: creation; deletion; resizing; movement; minimization; maximization; activation; enablement; or an alteration in relative background/foreground order are detected for each graphic user interface and that information and the associated display device driver for each graphic user interface are coupled to a virtual device driver which facilitates interprocess communication between two or more graphic user interfaces, wherein the portion of the video display which is managed by each graphic user interface may be ascertained. Each separate display device driver is then coupled to a single display device, wherein multiple windows supported by different graphic user interfaces may be simultaneously presented.

Method and system for simultaneous presentation of multiple windows

A method of generating a boot image and using the boot image to restore a computer system having a processor, an operating system, physical memory, virtual memory and disk storage. The method may be initiated from any particular software application, or at multiple execution points within a particular application. One or more boot images may be stored in association with an initiating application. By providing full virtual memory support in the boot image, the computer system may be restored to any predetermined operating state.

Software-enabled fast boot

A method and apparatus are disclosed for providing exchange of data between a peripheral device having a paging mechanism and an application operating in a virtual machine which includes a page directory for exclusive use by the paging mechanism of the peripheral device. The virtual machine is running on a data processing system and preferably contains a block of memory which is divided into various sections of memory. The page directory is provided to the paging mechanism of the peripheral device when the application requires the use of the peripheral device. A section of memory is selectively locked down in response to the section of memory being utilized by the application. Additionally, the page directory is updated with an entry which identifies the section of memory that is locked down. Memory may also be locked down in order to permit the peripheral device to access that section of memory. The page directory is selectively updated thereafter by mapping entries into the page directory in order to track memory usage within the block of memory utilized by the virtual machine. The page directory is preferably created at the same time the virtual machine is created. Memory for utilization by the virtual machine is preferably locked down while the virtual machine is in the foreground. When the virtual machine is terminated or moved into the background, the sections of memory that have been locked down are then unlocked or freed for other use.

System for locking down part of portion of memory and updating page

A method and apparatus for the enhancing efficiency of a data processing system which includes a host microprocessor, a system memory, and a graphics adapter for producing an enhanced graphics display. The graphics adapter is coupled to the data processing system by a bus and includes a video memory and an adapter microprocessor, wherein the adapter microprocessor is less powerful than the host microprocessor in the data processing system. The method and apparatus of the present invention includes the establishment of a stage buffer from a portion of the system memory with the stage buffer, including at least two buffer sections. A first portion of data is transferred from the system memory into a first buffer section. Next, a second portion of data is transferred from the system memory into a second buffer section, while the adapter microprocessor is simultaneously retrieving the first portion of data from the first buffer section and transferring that first portion of data across the bus to the video memory, wherein host microprocessor is available to perform other tasks. When the adapter microprocessor has transferred the data to the video memory from the first buffer section, the host microprocessor fills the first buffer section with more data, while the adapter microprocessor retrieves data from the second buffer section. This process continues until all the data has been transferred.

System for transferring data between processors via dual buffers within

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Austin, TX, United States of America

Tatchi Placido Lay