Seiko Epson Corporation

Juniper Networks, Inc.

S-mos Systems, Inc.

Tatao Chuang

Chong Ming Lin

Hy Hoang

Tran Long

Philippe Lacroute

Gerald Cheung

Pankaj Patel

Chi-Chung Kenny Chen

Dennis C Ferguson

Pradeep S Sindhu

Avanindra Godbole

Debashis Basu

Jeffrey Glenn Libby

Raymond Lim

Viswesh Ananthakrishnan

Devereaux C Chen

Viswesh Anathakrishnan

Visweh Ananthakrishnan

Dennis Fersuson

Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of 'virtual queues' corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue.

Maintaining packet order using hash-based linked-list queues

A network device constructs a notification corresponding to a received multicast data unit, where the notification includes administrative data associated with the multicast data unit that does not include a payload of the multicast data unit. The network device replicates the notification at least three different processing elements at different locations in a processing path of the network device to produce multiple replicated data items and produces a copy of the multicast data unit for each of replicated notifications. The network device forwards each copy of the multicast data unit towards a multicast destination.

Systems and methods for efficient multicast handling

A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

Method for manufacturing a power bus on a chip

A network device includes an interface and packet processing logic. The interface receives a multicast packet. The packet processing logic determines identifier data corresponding to the received multicast packet and replicates the identifier data to multiple outgoing packet forward engines at a first point in a processing path. The packet processing logic further replicates the identifier data to multiple data streams at a second point in the processing path and replicates the identifier data to multiple logical interfaces in the same stream at a third point in the processing path.

A system for monitoring internal states of an integrated circuit includes logic nodes, selection logic and a monitor unit. The logic nodes are disposed within the integrated circuit and the selection logic is coupled to monitor pins externally accessible on the integrated circuit. The selection logic retrieves internal states of select logic nodes based on signals applied via the monitor pins. The monitor unit reads the internal states of the select logic nodes via the monitor pins.

Systems and methods for monitoring integrated circuit internal states

Computer program product for defining slits in a bus on a chip

Power bus and method for generating power slits therein

An automatic method of generating slits in power buses on a chip. The present invention includes three embodiments. The first embodiment is directed to a generic method of generating power slits. Once bus dimensions are identified, predetermined parameters for optimal power slit size and number are used to automatically generate a power slit layer for the mask database. The second embodiment is a continuation of the first embodiment and is directed to a method of generating power slits for an orthogonal corner case; where two buses overlap at 90.degree. angles. This is performed by locating all corner cases. Power slits are removed within a cross (corner/intersect) area of overlapping buses. At this point power slits from overlapping buses are extended across the corner/intersect area. The extension lines are logically ANDed together/resulting in points within the corner/intersect area where the extension lines intersect. These intersection points indicate where new types of power slits, called 'holes', can be generated. The third embodiment is directed to a method of generating power slits for non-orthogonal corner case. It is generally identical to the second embodiment.

Power bus having power slits embodied therein and method for making the

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San Jose, CA, United States of America

Tatao Chuang